1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_DEF_H 8 #define TEGRA_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * Chip specific page table and MMU setup constants 14 ******************************************************************************/ 15 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40) 16 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40) 17 18 /******************************************************************************* 19 * These values are used by the PSCI implementation during the `CPU_SUSPEND` 20 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 21 * parameter. 22 ******************************************************************************/ 23 #define PSTATE_ID_CORE_IDLE U(6) 24 #define PSTATE_ID_CORE_POWERDN U(7) 25 #define PSTATE_ID_SOC_POWERDN U(2) 26 27 /******************************************************************************* 28 * Platform power states (used by PSCI framework) 29 * 30 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 31 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 32 ******************************************************************************/ 33 #define PLAT_MAX_RET_STATE U(1) 34 #define PLAT_MAX_OFF_STATE U(8) 35 36 /******************************************************************************* 37 * Secure IRQ definitions 38 ******************************************************************************/ 39 #define TEGRA194_MAX_SEC_IRQS U(2) 40 #define TEGRA194_TOP_WDT_IRQ U(49) 41 #define TEGRA194_AON_WDT_IRQ U(50) 42 43 #define TEGRA194_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */ 44 45 /******************************************************************************* 46 * Tegra Miscellanous register constants 47 ******************************************************************************/ 48 #define TEGRA_MISC_BASE U(0x00100000) 49 50 #define HARDWARE_REVISION_OFFSET U(0x4) 51 #define MISCREG_EMU_REVID U(0x3160) 52 #define BOARD_MASK_BITS U(0xFF) 53 #define BOARD_SHIFT_BITS U(24) 54 #define MISCREG_PFCFG U(0x200C) 55 56 /******************************************************************************* 57 * Tegra General Purpose Centralised DMA constants 58 ******************************************************************************/ 59 #define TEGRA_GPCDMA_BASE U(0x02610000) 60 61 /******************************************************************************* 62 * Tegra Memory Controller constants 63 ******************************************************************************/ 64 #define TEGRA_MC_STREAMID_BASE U(0x02C00000) 65 #define TEGRA_MC_BASE U(0x02C10000) 66 67 /* General Security Carveout register macros */ 68 #define MC_GSC_CONFIG_REGS_SIZE U(0x40) 69 #define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1) 70 #define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0) 71 #define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27) 72 #define MC_GSC_BASE_LO_SHIFT U(12) 73 #define MC_GSC_BASE_LO_MASK U(0xFFFFF) 74 #define MC_GSC_BASE_HI_SHIFT U(0) 75 #define MC_GSC_BASE_HI_MASK U(3) 76 #define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31) 77 78 /* TZDRAM carveout configuration registers */ 79 #define MC_SECURITY_CFG0_0 U(0x70) 80 #define MC_SECURITY_CFG1_0 U(0x74) 81 #define MC_SECURITY_CFG3_0 U(0x9BC) 82 83 #define MC_SECURITY_BOM_MASK (U(0xFFF) << 20) 84 #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) 85 #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) 86 87 #define MC_SECURITY_CFG_REG_CTRL_0 U(0x154) 88 #define SECURITY_CFG_WRITE_ACCESS_BIT (U(0x1) << 0) 89 #define SECURITY_CFG_WRITE_ACCESS_ENABLE U(0x0) 90 #define SECURITY_CFG_WRITE_ACCESS_DISABLE U(0x1) 91 92 /* Video Memory carveout configuration registers */ 93 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 94 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 95 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 96 97 /* 98 * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the 99 * non-overlapping Video memory region 100 */ 101 #define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0) 102 #define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4) 103 #define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8) 104 #define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC) 105 #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0) 106 107 /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 108 #define MC_TZRAM_CARVEOUT_CFG U(0x2190) 109 #define MC_TZRAM_BASE_LO U(0x2194) 110 #define MC_TZRAM_BASE_HI U(0x2198) 111 #define MC_TZRAM_SIZE U(0x219C) 112 #define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0) 113 #define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4) 114 #define TZRAM_ALLOW_MPCORER (U(1) << 7) 115 #define TZRAM_ALLOW_MPCOREW (U(1) << 25) 116 117 /* Memory Controller Reset Control registers */ 118 #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (U(1) << 28) 119 #define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (U(1) << 29) 120 #define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (U(1) << 30) 121 #define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (U(1) << 31) 122 123 /******************************************************************************* 124 * Tegra UART Controller constants 125 ******************************************************************************/ 126 #define TEGRA_UARTA_BASE U(0x03100000) 127 #define TEGRA_UARTB_BASE U(0x03110000) 128 #define TEGRA_UARTC_BASE U(0x0C280000) 129 #define TEGRA_UARTD_BASE U(0x03130000) 130 #define TEGRA_UARTE_BASE U(0x03140000) 131 #define TEGRA_UARTF_BASE U(0x03150000) 132 #define TEGRA_UARTG_BASE U(0x0C290000) 133 134 /******************************************************************************* 135 * XUSB PADCTL 136 ******************************************************************************/ 137 #define TEGRA_XUSB_PADCTL_BASE U(0x03520000) 138 #define TEGRA_XUSB_PADCTL_SIZE U(0x10000) 139 #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c) 140 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370) 141 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374) 142 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378) 143 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c) 144 #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c) 145 146 /******************************************************************************* 147 * Tegra Fuse Controller related constants 148 ******************************************************************************/ 149 #define TEGRA_FUSE_BASE U(0x03820000) 150 #define OPT_SUBREVISION U(0x248) 151 #define SUBREVISION_MASK U(0xF) 152 153 /******************************************************************************* 154 * GICv2 & interrupt handling related constants 155 ******************************************************************************/ 156 #define TEGRA_GICD_BASE U(0x03881000) 157 #define TEGRA_GICC_BASE U(0x03882000) 158 159 /******************************************************************************* 160 * Security Engine related constants 161 ******************************************************************************/ 162 #define TEGRA_SE0_BASE U(0x03AC0000) 163 #define SE0_MUTEX_WATCHDOG_NS_LIMIT U(0x6C) 164 #define SE0_AES0_ENTROPY_SRC_AGE_CTRL U(0x2FC) 165 #define TEGRA_PKA1_BASE U(0x03AD0000) 166 #define SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL U(0x144) 167 #define PKA1_MUTEX_WATCHDOG_NS_LIMIT SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL 168 #define TEGRA_RNG1_BASE U(0x03AE0000) 169 #define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) 170 171 /******************************************************************************* 172 * Tegra HSP doorbell #0 constants 173 ******************************************************************************/ 174 #define TEGRA_HSP_DBELL_BASE U(0x03C90000) 175 #define HSP_DBELL_1_ENABLE U(0x104) 176 #define HSP_DBELL_3_TRIGGER U(0x300) 177 #define HSP_DBELL_3_ENABLE U(0x304) 178 179 /******************************************************************************* 180 * Tegra hardware synchronization primitives for the SPE engine 181 ******************************************************************************/ 182 #define TEGRA_AON_HSP_SM_6_7_BASE U(0x0c190000) 183 #define TEGRA_CONSOLE_SPE_BASE (TEGRA_AON_HSP_SM_6_7_BASE + U(0x8000)) 184 185 /******************************************************************************* 186 * Tegra micro-seconds timer constants 187 ******************************************************************************/ 188 #define TEGRA_TMRUS_BASE U(0x0C2E0000) 189 #define TEGRA_TMRUS_SIZE U(0x10000) 190 191 /******************************************************************************* 192 * Tegra Power Mgmt Controller constants 193 ******************************************************************************/ 194 #define TEGRA_PMC_BASE U(0x0C360000) 195 196 /******************************************************************************* 197 * Tegra scratch registers constants 198 ******************************************************************************/ 199 #define TEGRA_SCRATCH_BASE U(0x0C390000) 200 #define SECURE_SCRATCH_RSV75 U(0x2BC) 201 #define SECURE_SCRATCH_RSV81_LO U(0x2EC) 202 #define SECURE_SCRATCH_RSV81_HI U(0x2F0) 203 #define SECURE_SCRATCH_RSV97 U(0x36C) 204 #define SECURE_SCRATCH_RSV99_LO U(0x37C) 205 #define SECURE_SCRATCH_RSV99_HI U(0x380) 206 #define SECURE_SCRATCH_RSV109_LO U(0x3CC) 207 #define SECURE_SCRATCH_RSV109_HI U(0x3D0) 208 209 #define SCRATCH_BL31_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75 210 #define SCRATCH_BL31_PARAMS_HI_ADDR_MASK U(0xFFFF) 211 #define SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT U(0) 212 #define SCRATCH_BL31_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_LO 213 #define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75 214 #define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK U(0xFFFF0000) 215 #define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT U(16) 216 #define SCRATCH_BL31_PLAT_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_HI 217 #define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97 218 #define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO 219 #define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI 220 #define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO 221 #define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI 222 223 /******************************************************************************* 224 * Tegra Memory Mapped Control Register Access Bus constants 225 ******************************************************************************/ 226 #define TEGRA_MMCRAB_BASE U(0x0E000000) 227 228 /******************************************************************************* 229 * Tegra SMMU Controller constants 230 ******************************************************************************/ 231 #define TEGRA_SMMU0_BASE U(0x12000000) 232 #define TEGRA_SMMU1_BASE U(0x11000000) 233 #define TEGRA_SMMU2_BASE U(0x10000000) 234 235 /******************************************************************************* 236 * Tegra TZRAM constants 237 ******************************************************************************/ 238 #define TEGRA_TZRAM_BASE U(0x40000000) 239 #define TEGRA_TZRAM_SIZE U(0x40000) 240 241 /******************************************************************************* 242 * Tegra CCPLEX-BPMP IPC constants 243 ******************************************************************************/ 244 #define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x4004C000) 245 #define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x4004D000) 246 #define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */ 247 248 /******************************************************************************* 249 * Tegra Clock and Reset Controller constants 250 ******************************************************************************/ 251 #define TEGRA_CAR_RESET_BASE U(0x20000000) 252 #define TEGRA_GPU_RESET_REG_OFFSET U(0x18) 253 #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x1C) 254 #define GPU_RESET_BIT (U(1) << 0) 255 #define GPU_SET_BIT (U(1) << 0) 256 #define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004) 257 #define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) 258 259 /******************************************************************************* 260 * Tegra DRAM memory base address 261 ******************************************************************************/ 262 #define TEGRA_DRAM_BASE ULL(0x80000000) 263 #define TEGRA_DRAM_END ULL(0xFFFFFFFFF) 264 265 /******************************************************************************* 266 * XUSB STREAMIDs 267 ******************************************************************************/ 268 #define TEGRA_SID_XUSB_HOST U(0x1b) 269 #define TEGRA_SID_XUSB_DEV U(0x1c) 270 #define TEGRA_SID_XUSB_VF0 U(0x5d) 271 #define TEGRA_SID_XUSB_VF1 U(0x5e) 272 #define TEGRA_SID_XUSB_VF2 U(0x5f) 273 #define TEGRA_SID_XUSB_VF3 U(0x60) 274 275 #endif /* TEGRA_DEF_H */ 276