1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_DEF_H 8 #define TEGRA_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * Chip specific page table and MMU setup constants 14 ******************************************************************************/ 15 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40) 16 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40) 17 18 /******************************************************************************* 19 * These values are used by the PSCI implementation during the `CPU_SUSPEND` 20 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 21 * parameter. 22 ******************************************************************************/ 23 #define PSTATE_ID_CORE_IDLE U(6) 24 #define PSTATE_ID_CORE_POWERDN U(7) 25 #define PSTATE_ID_SOC_POWERDN U(2) 26 27 /******************************************************************************* 28 * Platform power states (used by PSCI framework) 29 * 30 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 31 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 32 ******************************************************************************/ 33 #define PLAT_MAX_RET_STATE U(1) 34 #define PLAT_MAX_OFF_STATE U(8) 35 36 /******************************************************************************* 37 * Secure IRQ definitions 38 ******************************************************************************/ 39 #define TEGRA194_MAX_SEC_IRQS U(2) 40 #define TEGRA194_TOP_WDT_IRQ U(49) 41 #define TEGRA194_AON_WDT_IRQ U(50) 42 43 #define TEGRA194_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */ 44 45 /******************************************************************************* 46 * Clock identifier for the SE device 47 ******************************************************************************/ 48 #define TEGRA194_CLK_SE U(124) 49 #define TEGRA_CLK_SE TEGRA194_CLK_SE 50 51 /******************************************************************************* 52 * Tegra Miscellanous register constants 53 ******************************************************************************/ 54 #define TEGRA_MISC_BASE U(0x00100000) 55 56 #define HARDWARE_REVISION_OFFSET U(0x4) 57 #define MISCREG_EMU_REVID U(0x3160) 58 #define BOARD_MASK_BITS U(0xFF) 59 #define BOARD_SHIFT_BITS U(24) 60 #define MISCREG_PFCFG U(0x200C) 61 62 /******************************************************************************* 63 * Tegra General Purpose Centralised DMA constants 64 ******************************************************************************/ 65 #define TEGRA_GPCDMA_BASE U(0x02610000) 66 67 /******************************************************************************* 68 * Tegra Memory Controller constants 69 ******************************************************************************/ 70 #define TEGRA_MC_STREAMID_BASE U(0x02C00000) 71 #define TEGRA_MC_BASE U(0x02C10000) 72 73 /* General Security Carveout register macros */ 74 #define MC_GSC_CONFIG_REGS_SIZE U(0x40) 75 #define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1) 76 #define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0) 77 #define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27) 78 #define MC_GSC_BASE_LO_SHIFT U(12) 79 #define MC_GSC_BASE_LO_MASK U(0xFFFFF) 80 #define MC_GSC_BASE_HI_SHIFT U(0) 81 #define MC_GSC_BASE_HI_MASK U(3) 82 #define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31) 83 84 /* TZDRAM carveout configuration registers */ 85 #define MC_SECURITY_CFG0_0 U(0x70) 86 #define MC_SECURITY_CFG1_0 U(0x74) 87 #define MC_SECURITY_CFG3_0 U(0x9BC) 88 89 #define MC_SECURITY_BOM_MASK (U(0xFFF) << 20) 90 #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) 91 #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) 92 93 #define MC_SECURITY_CFG_REG_CTRL_0 U(0x154) 94 #define SECURITY_CFG_WRITE_ACCESS_BIT (U(0x1) << 0) 95 #define SECURITY_CFG_WRITE_ACCESS_ENABLE U(0x0) 96 #define SECURITY_CFG_WRITE_ACCESS_DISABLE U(0x1) 97 98 /* Video Memory carveout configuration registers */ 99 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 100 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 101 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 102 103 /* 104 * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the 105 * non-overlapping Video memory region 106 */ 107 #define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0) 108 #define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4) 109 #define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8) 110 #define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC) 111 #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0) 112 113 /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 114 #define MC_TZRAM_CARVEOUT_CFG U(0x2190) 115 #define MC_TZRAM_BASE_LO U(0x2194) 116 #define MC_TZRAM_BASE_HI U(0x2198) 117 #define MC_TZRAM_SIZE U(0x219C) 118 #define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0) 119 #define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4) 120 #define TZRAM_ALLOW_MPCORER (U(1) << 7) 121 #define TZRAM_ALLOW_MPCOREW (U(1) << 25) 122 123 /* Memory Controller Reset Control registers */ 124 #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (U(1) << 28) 125 #define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (U(1) << 29) 126 #define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (U(1) << 30) 127 #define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (U(1) << 31) 128 129 /******************************************************************************* 130 * Tegra UART Controller constants 131 ******************************************************************************/ 132 #define TEGRA_UARTA_BASE U(0x03100000) 133 #define TEGRA_UARTB_BASE U(0x03110000) 134 #define TEGRA_UARTC_BASE U(0x0C280000) 135 #define TEGRA_UARTD_BASE U(0x03130000) 136 #define TEGRA_UARTE_BASE U(0x03140000) 137 #define TEGRA_UARTF_BASE U(0x03150000) 138 #define TEGRA_UARTG_BASE U(0x0C290000) 139 140 /******************************************************************************* 141 * XUSB PADCTL 142 ******************************************************************************/ 143 #define TEGRA_XUSB_PADCTL_BASE U(0x03520000) 144 #define TEGRA_XUSB_PADCTL_SIZE U(0x10000) 145 #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c) 146 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370) 147 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374) 148 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378) 149 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c) 150 #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c) 151 152 /******************************************************************************* 153 * Tegra Fuse Controller related constants 154 ******************************************************************************/ 155 #define TEGRA_FUSE_BASE U(0x03820000) 156 #define OPT_SUBREVISION U(0x248) 157 #define SUBREVISION_MASK U(0xF) 158 159 /******************************************************************************* 160 * GICv2 & interrupt handling related constants 161 ******************************************************************************/ 162 #define TEGRA_GICD_BASE U(0x03881000) 163 #define TEGRA_GICC_BASE U(0x03882000) 164 165 /******************************************************************************* 166 * Security Engine related constants 167 ******************************************************************************/ 168 #define TEGRA_SE0_BASE U(0x03AC0000) 169 #define SE0_MUTEX_WATCHDOG_NS_LIMIT U(0x6C) 170 #define SE0_AES0_ENTROPY_SRC_AGE_CTRL U(0x2FC) 171 #define TEGRA_PKA1_BASE U(0x03AD0000) 172 #define SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL U(0x144) 173 #define PKA1_MUTEX_WATCHDOG_NS_LIMIT SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL 174 #define TEGRA_RNG1_BASE U(0x03AE0000) 175 #define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) 176 177 /******************************************************************************* 178 * Tegra HSP doorbell #0 constants 179 ******************************************************************************/ 180 #define TEGRA_HSP_DBELL_BASE U(0x03C90000) 181 #define HSP_DBELL_1_ENABLE U(0x104) 182 #define HSP_DBELL_3_TRIGGER U(0x300) 183 #define HSP_DBELL_3_ENABLE U(0x304) 184 185 /******************************************************************************* 186 * Tegra hardware synchronization primitives for the SPE engine 187 ******************************************************************************/ 188 #define TEGRA_AON_HSP_SM_6_7_BASE U(0x0c190000) 189 #define TEGRA_CONSOLE_SPE_BASE (TEGRA_AON_HSP_SM_6_7_BASE + U(0x8000)) 190 191 /******************************************************************************* 192 * Tegra micro-seconds timer constants 193 ******************************************************************************/ 194 #define TEGRA_TMRUS_BASE U(0x0C2E0000) 195 #define TEGRA_TMRUS_SIZE U(0x10000) 196 197 /******************************************************************************* 198 * Tegra Power Mgmt Controller constants 199 ******************************************************************************/ 200 #define TEGRA_PMC_BASE U(0x0C360000) 201 202 /******************************************************************************* 203 * Tegra scratch registers constants 204 ******************************************************************************/ 205 #define TEGRA_SCRATCH_BASE U(0x0C390000) 206 #define SECURE_SCRATCH_RSV68_LO U(0x284) 207 #define SECURE_SCRATCH_RSV68_HI U(0x288) 208 #define SECURE_SCRATCH_RSV69_LO U(0x28C) 209 #define SECURE_SCRATCH_RSV69_HI U(0x290) 210 #define SECURE_SCRATCH_RSV70_LO U(0x294) 211 #define SECURE_SCRATCH_RSV70_HI U(0x298) 212 #define SECURE_SCRATCH_RSV71_LO U(0x29C) 213 #define SECURE_SCRATCH_RSV71_HI U(0x2A0) 214 #define SECURE_SCRATCH_RSV72_LO U(0x2A4) 215 #define SECURE_SCRATCH_RSV72_HI U(0x2A8) 216 #define SECURE_SCRATCH_RSV75 U(0x2BC) 217 #define SECURE_SCRATCH_RSV81_LO U(0x2EC) 218 #define SECURE_SCRATCH_RSV81_HI U(0x2F0) 219 #define SECURE_SCRATCH_RSV97 U(0x36C) 220 #define SECURE_SCRATCH_RSV99_LO U(0x37C) 221 #define SECURE_SCRATCH_RSV99_HI U(0x380) 222 #define SECURE_SCRATCH_RSV109_LO U(0x3CC) 223 #define SECURE_SCRATCH_RSV109_HI U(0x3D0) 224 225 #define SCRATCH_BL31_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75 226 #define SCRATCH_BL31_PARAMS_HI_ADDR_MASK U(0xFFFF) 227 #define SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT U(0) 228 #define SCRATCH_BL31_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_LO 229 #define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75 230 #define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK U(0xFFFF0000) 231 #define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT U(16) 232 #define SCRATCH_BL31_PLAT_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_HI 233 #define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97 234 #define SCRATCH_MC_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO 235 #define SCRATCH_MC_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI 236 #define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO 237 #define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI 238 239 /******************************************************************************* 240 * Tegra Memory Mapped Control Register Access Bus constants 241 ******************************************************************************/ 242 #define TEGRA_MMCRAB_BASE U(0x0E000000) 243 244 /******************************************************************************* 245 * Tegra SMMU Controller constants 246 ******************************************************************************/ 247 #define TEGRA_SMMU0_BASE U(0x12000000) 248 #define TEGRA_SMMU1_BASE U(0x11000000) 249 #define TEGRA_SMMU2_BASE U(0x10000000) 250 251 /******************************************************************************* 252 * Tegra TZRAM constants 253 ******************************************************************************/ 254 #define TEGRA_TZRAM_BASE U(0x40000000) 255 #define TEGRA_TZRAM_SIZE U(0x40000) 256 257 /******************************************************************************* 258 * Tegra CCPLEX-BPMP IPC constants 259 ******************************************************************************/ 260 #define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x4004C000) 261 #define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x4004D000) 262 #define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */ 263 264 /******************************************************************************* 265 * Tegra Clock and Reset Controller constants 266 ******************************************************************************/ 267 #define TEGRA_CAR_RESET_BASE U(0x20000000) 268 #define TEGRA_GPU_RESET_REG_OFFSET U(0x18) 269 #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x1C) 270 #define GPU_RESET_BIT (U(1) << 0) 271 #define GPU_SET_BIT (U(1) << 0) 272 #define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004) 273 #define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) 274 275 /******************************************************************************* 276 * Tegra DRAM memory base address 277 ******************************************************************************/ 278 #define TEGRA_DRAM_BASE ULL(0x80000000) 279 #define TEGRA_DRAM_END ULL(0xFFFFFFFFF) 280 281 /******************************************************************************* 282 * XUSB STREAMIDs 283 ******************************************************************************/ 284 #define TEGRA_SID_XUSB_HOST U(0x1b) 285 #define TEGRA_SID_XUSB_DEV U(0x1c) 286 #define TEGRA_SID_XUSB_VF0 U(0x5d) 287 #define TEGRA_SID_XUSB_VF1 U(0x5e) 288 #define TEGRA_SID_XUSB_VF2 U(0x5f) 289 #define TEGRA_SID_XUSB_VF3 U(0x60) 290 291 #endif /* TEGRA_DEF_H */ 292