141612559SVarun Wadekar /* 241612559SVarun Wadekar * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 341612559SVarun Wadekar * 441612559SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 541612559SVarun Wadekar */ 641612559SVarun Wadekar 741612559SVarun Wadekar #ifndef __TEGRA_DEF_H__ 841612559SVarun Wadekar #define __TEGRA_DEF_H__ 941612559SVarun Wadekar 1041612559SVarun Wadekar #include <lib/utils_def.h> 1141612559SVarun Wadekar 1241612559SVarun Wadekar /******************************************************************************* 1341612559SVarun Wadekar * These values are used by the PSCI implementation during the `CPU_SUSPEND` 1441612559SVarun Wadekar * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 1541612559SVarun Wadekar * parameter. 1641612559SVarun Wadekar ******************************************************************************/ 1741612559SVarun Wadekar #define PSTATE_ID_CORE_IDLE 6 1841612559SVarun Wadekar #define PSTATE_ID_CORE_POWERDN 7 1941612559SVarun Wadekar #define PSTATE_ID_SOC_POWERDN 2 2041612559SVarun Wadekar 2141612559SVarun Wadekar /******************************************************************************* 2241612559SVarun Wadekar * Platform power states (used by PSCI framework) 2341612559SVarun Wadekar * 2441612559SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 2541612559SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 2641612559SVarun Wadekar ******************************************************************************/ 2741612559SVarun Wadekar #define PLAT_MAX_RET_STATE 1 2841612559SVarun Wadekar #define PLAT_MAX_OFF_STATE 8 2941612559SVarun Wadekar 3041612559SVarun Wadekar /******************************************************************************* 3141612559SVarun Wadekar * Secure IRQ definitions 3241612559SVarun Wadekar ******************************************************************************/ 3341612559SVarun Wadekar #define TEGRA186_MAX_SEC_IRQS 5 3441612559SVarun Wadekar #define TEGRA186_BPMP_WDT_IRQ 46 3541612559SVarun Wadekar #define TEGRA186_SPE_WDT_IRQ 47 3641612559SVarun Wadekar #define TEGRA186_SCE_WDT_IRQ 48 3741612559SVarun Wadekar #define TEGRA186_TOP_WDT_IRQ 49 3841612559SVarun Wadekar #define TEGRA186_AON_WDT_IRQ 50 3941612559SVarun Wadekar 4041612559SVarun Wadekar #define TEGRA186_SEC_IRQ_TARGET_MASK 0xFF /* 8 Carmel */ 4141612559SVarun Wadekar 4241612559SVarun Wadekar /******************************************************************************* 4341612559SVarun Wadekar * Tegra Miscellanous register constants 4441612559SVarun Wadekar ******************************************************************************/ 4513dcbc6fSSteven Kao #define TEGRA_MISC_BASE 0x00100000U 4641612559SVarun Wadekar 4713dcbc6fSSteven Kao #define HARDWARE_REVISION_OFFSET 0x4U 4813dcbc6fSSteven Kao #define MISCREG_EMU_REVID 0x3160U 4913dcbc6fSSteven Kao #define BOARD_MASK_BITS 0xFFU 5013dcbc6fSSteven Kao #define BOARD_SHIFT_BITS 24U 5113dcbc6fSSteven Kao #define MISCREG_PFCFG 0x200CU 5241612559SVarun Wadekar 5341612559SVarun Wadekar /******************************************************************************* 5441612559SVarun Wadekar * Tegra TSA Controller constants 5541612559SVarun Wadekar ******************************************************************************/ 5641612559SVarun Wadekar #define TEGRA_TSA_BASE 0x02000000 5741612559SVarun Wadekar 5841612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SESWR 0x1010 5941612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 6041612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_ETRW 0xD034 6141612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 6241612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x3020 6341612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 6441612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AXISW 0x8008 6541612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 6641612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_HDAW 0xD008 6741612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x1100 6841612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xE018 6941612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 7041612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x9008 7141612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 7241612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9028 7341612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 7441612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xB008 7541612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 7641612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6008 7741612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 7841612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AFIW 0xF008 7941612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 8041612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SATAW 0x4008 8141612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 8241612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_EQOSW 0x3038 8341612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 8441612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x6018 8541612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 8641612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x6028 8741612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 8841612559SVarun Wadekar 8941612559SVarun Wadekar #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) 9041612559SVarun Wadekar #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) 9141612559SVarun Wadekar 9241612559SVarun Wadekar /******************************************************************************* 9341612559SVarun Wadekar * Tegra Memory Controller constants 9441612559SVarun Wadekar ******************************************************************************/ 9541612559SVarun Wadekar #define TEGRA_MC_STREAMID_BASE 0x02C00000 9641612559SVarun Wadekar #define TEGRA_MC_BASE 0x02C10000 9741612559SVarun Wadekar 983b2b3375SVarun Wadekar /* General Security Carveout register macros */ 993b2b3375SVarun Wadekar #define MC_GSC_CONFIG_REGS_SIZE 0x40 1003b2b3375SVarun Wadekar #define MC_GSC_LOCK_CFG_SETTINGS_BIT (1 << 1) 1013b2b3375SVarun Wadekar #define MC_GSC_ENABLE_TZ_LOCK_BIT (1 << 0) 1023b2b3375SVarun Wadekar #define MC_GSC_SIZE_RANGE_4KB_SHIFT 27 1033b2b3375SVarun Wadekar #define MC_GSC_BASE_LO_SHIFT 12 1043b2b3375SVarun Wadekar #define MC_GSC_BASE_LO_MASK 0xFFFFF 1053b2b3375SVarun Wadekar #define MC_GSC_BASE_HI_SHIFT 0 1063b2b3375SVarun Wadekar #define MC_GSC_BASE_HI_MASK 3 1073b2b3375SVarun Wadekar 10841612559SVarun Wadekar /* TZDRAM carveout configuration registers */ 10941612559SVarun Wadekar #define MC_SECURITY_CFG0_0 0x70 11041612559SVarun Wadekar #define MC_SECURITY_CFG1_0 0x74 11141612559SVarun Wadekar #define MC_SECURITY_CFG3_0 0x9BC 11241612559SVarun Wadekar 11341612559SVarun Wadekar /* Video Memory carveout configuration registers */ 11441612559SVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI 0x978 11541612559SVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO 0x648 11641612559SVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 11741612559SVarun Wadekar 1183b2b3375SVarun Wadekar /* 1193b2b3375SVarun Wadekar * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the 1203b2b3375SVarun Wadekar * non-overlapping Video memory region 1213b2b3375SVarun Wadekar */ 1223b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0 1233b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4 1243b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8 1253b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC 1263b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0 1273b2b3375SVarun Wadekar 12841612559SVarun Wadekar /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 12941612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_CFG 0x2190 1303b2b3375SVarun Wadekar #define MC_TZRAM_BASE_LO 0x2194 1313b2b3375SVarun Wadekar #define MC_TZRAM_BASE_HI 0x2198 1323b2b3375SVarun Wadekar #define MC_TZRAM_SIZE 0x219C 1333b2b3375SVarun Wadekar #define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0 13441612559SVarun Wadekar 13541612559SVarun Wadekar /* Memory Controller Reset Control registers */ 13641612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1 << 27) 13741612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28) 13841612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29) 13941612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30) 14041612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (1 << 31) 14141612559SVarun Wadekar 14241612559SVarun Wadekar /******************************************************************************* 14341612559SVarun Wadekar * Tegra UART Controller constants 14441612559SVarun Wadekar ******************************************************************************/ 14541612559SVarun Wadekar #define TEGRA_UARTA_BASE 0x03100000 14641612559SVarun Wadekar #define TEGRA_UARTB_BASE 0x03110000 14741612559SVarun Wadekar #define TEGRA_UARTC_BASE 0x0C280000 14841612559SVarun Wadekar #define TEGRA_UARTD_BASE 0x03130000 14941612559SVarun Wadekar #define TEGRA_UARTE_BASE 0x03140000 15041612559SVarun Wadekar #define TEGRA_UARTF_BASE 0x03150000 15141612559SVarun Wadekar #define TEGRA_UARTG_BASE 0x0C290000 15241612559SVarun Wadekar 15341612559SVarun Wadekar /******************************************************************************* 15441612559SVarun Wadekar * Tegra Fuse Controller related constants 15541612559SVarun Wadekar ******************************************************************************/ 15641612559SVarun Wadekar #define TEGRA_FUSE_BASE 0x03820000 15741612559SVarun Wadekar #define OPT_SUBREVISION 0x248 15841612559SVarun Wadekar #define SUBREVISION_MASK 0xF 15941612559SVarun Wadekar 16041612559SVarun Wadekar /******************************************************************************* 16141612559SVarun Wadekar * GICv2 & interrupt handling related constants 16241612559SVarun Wadekar ******************************************************************************/ 16341612559SVarun Wadekar #define TEGRA_GICD_BASE 0x03881000 16441612559SVarun Wadekar #define TEGRA_GICC_BASE 0x03882000 16541612559SVarun Wadekar 16641612559SVarun Wadekar /******************************************************************************* 16741612559SVarun Wadekar * Security Engine related constants 16841612559SVarun Wadekar ******************************************************************************/ 16941612559SVarun Wadekar #define TEGRA_SE0_BASE 0x03AC0000 17041612559SVarun Wadekar #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C 17141612559SVarun Wadekar #define TEGRA_PKA1_BASE 0x03AD0000 17241612559SVarun Wadekar #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 17341612559SVarun Wadekar #define TEGRA_RNG1_BASE 0x03AE0000 17441612559SVarun Wadekar #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 17541612559SVarun Wadekar 17641612559SVarun Wadekar /******************************************************************************* 17741612559SVarun Wadekar * Tegra micro-seconds timer constants 17841612559SVarun Wadekar ******************************************************************************/ 17941612559SVarun Wadekar #define TEGRA_TMRUS_BASE 0x0C2E0000 180d82f5a36SSteven Kao #define TEGRA_TMRUS_SIZE 0x10000 18141612559SVarun Wadekar 18241612559SVarun Wadekar /******************************************************************************* 18341612559SVarun Wadekar * Tegra Power Mgmt Controller constants 18441612559SVarun Wadekar ******************************************************************************/ 18541612559SVarun Wadekar #define TEGRA_PMC_BASE 0x0C360000 18641612559SVarun Wadekar 18741612559SVarun Wadekar /******************************************************************************* 18841612559SVarun Wadekar * Tegra scratch registers constants 18941612559SVarun Wadekar ******************************************************************************/ 19041612559SVarun Wadekar #define TEGRA_SCRATCH_BASE 0x0C390000 19141612559SVarun Wadekar #define SECURE_SCRATCH_RSV1_LO 0x06C 19241612559SVarun Wadekar #define SECURE_SCRATCH_RSV1_HI 0x070 19341612559SVarun Wadekar #define SECURE_SCRATCH_RSV6 0x094 19441612559SVarun Wadekar #define SECURE_SCRATCH_RSV11_LO 0x0BC 19541612559SVarun Wadekar #define SECURE_SCRATCH_RSV11_HI 0x0C0 19641612559SVarun Wadekar #define SECURE_SCRATCH_RSV53_LO 0x20C 19741612559SVarun Wadekar #define SECURE_SCRATCH_RSV53_HI 0x210 19841612559SVarun Wadekar #define SECURE_SCRATCH_RSV54_HI 0x218 19941612559SVarun Wadekar #define SECURE_SCRATCH_RSV55_LO 0x21C 20041612559SVarun Wadekar #define SECURE_SCRATCH_RSV55_HI 0x220 20141612559SVarun Wadekar 20241612559SVarun Wadekar /******************************************************************************* 20341612559SVarun Wadekar * Tegra Memory Mapped Control Register Access Bus constants 20441612559SVarun Wadekar ******************************************************************************/ 20541612559SVarun Wadekar #define TEGRA_MMCRAB_BASE 0x0E000000 20641612559SVarun Wadekar 20741612559SVarun Wadekar /******************************************************************************* 20841612559SVarun Wadekar * Tegra SMMU Controller constants 20941612559SVarun Wadekar ******************************************************************************/ 2100ea8881eSPritesh Raithatha #define TEGRA_SMMU0_BASE 0x12000000 2110ea8881eSPritesh Raithatha #define TEGRA_SMMU1_BASE 0x11000000 2120ea8881eSPritesh Raithatha #define TEGRA_SMMU2_BASE 0x10000000 21341612559SVarun Wadekar 21441612559SVarun Wadekar /******************************************************************************* 21541612559SVarun Wadekar * Tegra TZRAM constants 21641612559SVarun Wadekar ******************************************************************************/ 21741612559SVarun Wadekar #define TEGRA_TZRAM_BASE 0x40000000 21841612559SVarun Wadekar #define TEGRA_TZRAM_SIZE 0x40000 21941612559SVarun Wadekar 22041612559SVarun Wadekar /******************************************************************************* 22141612559SVarun Wadekar * Tegra Clock and Reset Controller constants 22241612559SVarun Wadekar ******************************************************************************/ 22341612559SVarun Wadekar #define TEGRA_CAR_RESET_BASE 0x200000000 2242fdd9ae6SVarun Wadekar #define TEGRA_GPU_RESET_REG_OFFSET 0x18UL 2252fdd9ae6SVarun Wadekar #define GPU_RESET_BIT (1UL << 0) 22641612559SVarun Wadekar 227719fdb6eSVarun Wadekar /******************************************************************************* 228719fdb6eSVarun Wadekar * Stream ID Override Config registers 229719fdb6eSVarun Wadekar ******************************************************************************/ 230719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U 231719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U 232719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U 233719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U 234719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U 235719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U 236719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U 237719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U 238719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U 239719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U 240719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U 241719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5E0U 242719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5E8U 243719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5F0U 244719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5F8U 245719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U 246719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U 247719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U 248719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U 249719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U 250719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U 251719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U 252719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U 253719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U 254719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U 255719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U 256719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U 257719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U 258719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U 259719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U 260719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U 261719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U 262719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U 263719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U 264719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U 265719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6A0U 266719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6A8U 267719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6B0U 268719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6B8U 269719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6C0U 270719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6C8U 271719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6D0U 272719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6D8U 273719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6E0U 274719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6E8U 275719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6F0U 276719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6F8U 277719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U 278719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U 279719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U 280719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U 281719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U 282719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U 283719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U 284719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U 285719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U 286719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U 287719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U 288719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U 289719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U 290719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U 291719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U 292719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U 293719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7C8U 294719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7D0U 295719fdb6eSVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7D8U 296719fdb6eSVarun Wadekar 297719fdb6eSVarun Wadekar /******************************************************************************* 298719fdb6eSVarun Wadekar * Memory Controller transaction override config registers 299719fdb6eSVarun Wadekar ******************************************************************************/ 300719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530 301719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538 302719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540 303719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548 304719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570 305719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578 306719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580 307719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158C 308719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15E4 309719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15EC 310719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15F4 311719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15FC 312719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604 313719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160C 314719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614 315719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161C 316719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624 317719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162C 318719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634 319719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163C 320719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644 321719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164C 322719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654 323719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165C 324719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664 325719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166C 326719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674 327719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167C 328719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684 329719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168C 330719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694 331719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169C 332719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16A4 333719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16AC 334719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16B4 335719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16BC 336719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16C4 337719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16CC 338719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16D4 339719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16DC 340719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16E4 341719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16EC 342719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16F4 343719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16FC 344719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704 345719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170C 346719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714 347719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171C 348719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724 349719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174C 350719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754 351719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175C 352719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764 353719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176C 354719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774 355719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177C 356719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784 357719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178C 358719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794 359719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179C 360719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17CC 361719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17D4 362719fdb6eSVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17DC 363719fdb6eSVarun Wadekar 364*bc019041SAjay Gupta /******************************************************************************* 365*bc019041SAjay Gupta * XUSB PADCTL 366*bc019041SAjay Gupta ******************************************************************************/ 367*bc019041SAjay Gupta #define TEGRA_XUSB_PADCTL_BASE (0x3520000U) 368*bc019041SAjay Gupta #define TEGRA_XUSB_PADCTL_SIZE (0x10000U) 369*bc019041SAjay Gupta #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) 370*bc019041SAjay Gupta #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) 371*bc019041SAjay Gupta #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) 372*bc019041SAjay Gupta #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) 373*bc019041SAjay Gupta #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) 374*bc019041SAjay Gupta #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) 375*bc019041SAjay Gupta 376*bc019041SAjay Gupta /******************************************************************************* 377*bc019041SAjay Gupta * XUSB STREAMIDs 378*bc019041SAjay Gupta ******************************************************************************/ 379*bc019041SAjay Gupta #define TEGRA_SID_XUSB_HOST (0x1bU) 380*bc019041SAjay Gupta #define TEGRA_SID_XUSB_DEV (0x1cU) 381*bc019041SAjay Gupta #define TEGRA_SID_XUSB_VF0 (0x5dU) 382*bc019041SAjay Gupta #define TEGRA_SID_XUSB_VF1 (0x5eU) 383*bc019041SAjay Gupta #define TEGRA_SID_XUSB_VF2 (0x5fU) 384*bc019041SAjay Gupta #define TEGRA_SID_XUSB_VF3 (0x60U) 385*bc019041SAjay Gupta 38641612559SVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 387