1*41612559SVarun Wadekar /* 2*41612559SVarun Wadekar * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3*41612559SVarun Wadekar * 4*41612559SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5*41612559SVarun Wadekar */ 6*41612559SVarun Wadekar 7*41612559SVarun Wadekar #ifndef __TEGRA_DEF_H__ 8*41612559SVarun Wadekar #define __TEGRA_DEF_H__ 9*41612559SVarun Wadekar 10*41612559SVarun Wadekar #include <lib/utils_def.h> 11*41612559SVarun Wadekar 12*41612559SVarun Wadekar /******************************************************************************* 13*41612559SVarun Wadekar * These values are used by the PSCI implementation during the `CPU_SUSPEND` 14*41612559SVarun Wadekar * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 15*41612559SVarun Wadekar * parameter. 16*41612559SVarun Wadekar ******************************************************************************/ 17*41612559SVarun Wadekar #define PSTATE_ID_CORE_IDLE 6 18*41612559SVarun Wadekar #define PSTATE_ID_CORE_POWERDN 7 19*41612559SVarun Wadekar #define PSTATE_ID_SOC_POWERDN 2 20*41612559SVarun Wadekar 21*41612559SVarun Wadekar /******************************************************************************* 22*41612559SVarun Wadekar * Platform power states (used by PSCI framework) 23*41612559SVarun Wadekar * 24*41612559SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 25*41612559SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 26*41612559SVarun Wadekar ******************************************************************************/ 27*41612559SVarun Wadekar #define PLAT_MAX_RET_STATE 1 28*41612559SVarun Wadekar #define PLAT_MAX_OFF_STATE 8 29*41612559SVarun Wadekar 30*41612559SVarun Wadekar /******************************************************************************* 31*41612559SVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 32*41612559SVarun Wadekar ******************************************************************************/ 33*41612559SVarun Wadekar #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 34*41612559SVarun Wadekar #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 35*41612559SVarun Wadekar #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 36*41612559SVarun Wadekar #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 37*41612559SVarun Wadekar #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 38*41612559SVarun Wadekar #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 39*41612559SVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 40*41612559SVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 41*41612559SVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 42*41612559SVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 43*41612559SVarun Wadekar 44*41612559SVarun Wadekar /******************************************************************************* 45*41612559SVarun Wadekar * Secure IRQ definitions 46*41612559SVarun Wadekar ******************************************************************************/ 47*41612559SVarun Wadekar #define TEGRA186_MAX_SEC_IRQS 5 48*41612559SVarun Wadekar #define TEGRA186_BPMP_WDT_IRQ 46 49*41612559SVarun Wadekar #define TEGRA186_SPE_WDT_IRQ 47 50*41612559SVarun Wadekar #define TEGRA186_SCE_WDT_IRQ 48 51*41612559SVarun Wadekar #define TEGRA186_TOP_WDT_IRQ 49 52*41612559SVarun Wadekar #define TEGRA186_AON_WDT_IRQ 50 53*41612559SVarun Wadekar 54*41612559SVarun Wadekar #define TEGRA186_SEC_IRQ_TARGET_MASK 0xFF /* 8 Carmel */ 55*41612559SVarun Wadekar 56*41612559SVarun Wadekar /******************************************************************************* 57*41612559SVarun Wadekar * Tegra Miscellanous register constants 58*41612559SVarun Wadekar ******************************************************************************/ 59*41612559SVarun Wadekar #define TEGRA_MISC_BASE 0x00100000 60*41612559SVarun Wadekar #define HARDWARE_REVISION_OFFSET 0x4 61*41612559SVarun Wadekar 62*41612559SVarun Wadekar #define MISCREG_PFCFG 0x200C 63*41612559SVarun Wadekar 64*41612559SVarun Wadekar /******************************************************************************* 65*41612559SVarun Wadekar * Tegra TSA Controller constants 66*41612559SVarun Wadekar ******************************************************************************/ 67*41612559SVarun Wadekar #define TEGRA_TSA_BASE 0x02000000 68*41612559SVarun Wadekar 69*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SESWR 0x1010 70*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 71*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_ETRW 0xD034 72*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 73*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x3020 74*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 75*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AXISW 0x8008 76*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 77*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_HDAW 0xD008 78*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x1100 79*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xE018 80*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 81*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x9008 82*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 83*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9028 84*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 85*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xB008 86*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 87*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6008 88*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 89*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AFIW 0xF008 90*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 91*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SATAW 0x4008 92*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 93*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_EQOSW 0x3038 94*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 95*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x6018 96*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 97*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x6028 98*41612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 99*41612559SVarun Wadekar 100*41612559SVarun Wadekar #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) 101*41612559SVarun Wadekar #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) 102*41612559SVarun Wadekar 103*41612559SVarun Wadekar /******************************************************************************* 104*41612559SVarun Wadekar * Tegra Memory Controller constants 105*41612559SVarun Wadekar ******************************************************************************/ 106*41612559SVarun Wadekar #define TEGRA_MC_STREAMID_BASE 0x02C00000 107*41612559SVarun Wadekar #define TEGRA_MC_BASE 0x02C10000 108*41612559SVarun Wadekar 109*41612559SVarun Wadekar /* TZDRAM carveout configuration registers */ 110*41612559SVarun Wadekar #define MC_SECURITY_CFG0_0 0x70 111*41612559SVarun Wadekar #define MC_SECURITY_CFG1_0 0x74 112*41612559SVarun Wadekar #define MC_SECURITY_CFG3_0 0x9BC 113*41612559SVarun Wadekar 114*41612559SVarun Wadekar /* Video Memory carveout configuration registers */ 115*41612559SVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI 0x978 116*41612559SVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO 0x648 117*41612559SVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 118*41612559SVarun Wadekar 119*41612559SVarun Wadekar /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 120*41612559SVarun Wadekar #define MC_TZRAM_BASE_LO 0x2194 121*41612559SVarun Wadekar #define TZRAM_BASE_LO_SHIFT 12 122*41612559SVarun Wadekar #define TZRAM_BASE_LO_MASK 0xFFFFF 123*41612559SVarun Wadekar #define MC_TZRAM_BASE_HI 0x2198 124*41612559SVarun Wadekar #define TZRAM_BASE_HI_SHIFT 0 125*41612559SVarun Wadekar #define TZRAM_BASE_HI_MASK 3 126*41612559SVarun Wadekar #define MC_TZRAM_SIZE 0x219C 127*41612559SVarun Wadekar #define TZRAM_SIZE_RANGE_4KB_SHIFT 27 128*41612559SVarun Wadekar 129*41612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_CFG 0x2190 130*41612559SVarun Wadekar #define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1) 131*41612559SVarun Wadekar #define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0) 132*41612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0 133*41612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4 134*41612559SVarun Wadekar #define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25) 135*41612559SVarun Wadekar #define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7) 136*41612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8 137*41612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC 138*41612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0 139*41612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4 140*41612559SVarun Wadekar 141*41612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21C0 142*41612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21C4 143*41612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C8 144*41612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21CC 145*41612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21D0 146*41612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21D4 147*41612559SVarun Wadekar 148*41612559SVarun Wadekar /* Memory Controller Reset Control registers */ 149*41612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1 << 27) 150*41612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28) 151*41612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29) 152*41612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30) 153*41612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (1 << 31) 154*41612559SVarun Wadekar 155*41612559SVarun Wadekar /******************************************************************************* 156*41612559SVarun Wadekar * Tegra UART Controller constants 157*41612559SVarun Wadekar ******************************************************************************/ 158*41612559SVarun Wadekar #define TEGRA_UARTA_BASE 0x03100000 159*41612559SVarun Wadekar #define TEGRA_UARTB_BASE 0x03110000 160*41612559SVarun Wadekar #define TEGRA_UARTC_BASE 0x0C280000 161*41612559SVarun Wadekar #define TEGRA_UARTD_BASE 0x03130000 162*41612559SVarun Wadekar #define TEGRA_UARTE_BASE 0x03140000 163*41612559SVarun Wadekar #define TEGRA_UARTF_BASE 0x03150000 164*41612559SVarun Wadekar #define TEGRA_UARTG_BASE 0x0C290000 165*41612559SVarun Wadekar 166*41612559SVarun Wadekar /******************************************************************************* 167*41612559SVarun Wadekar * Tegra Fuse Controller related constants 168*41612559SVarun Wadekar ******************************************************************************/ 169*41612559SVarun Wadekar #define TEGRA_FUSE_BASE 0x03820000 170*41612559SVarun Wadekar #define OPT_SUBREVISION 0x248 171*41612559SVarun Wadekar #define SUBREVISION_MASK 0xF 172*41612559SVarun Wadekar 173*41612559SVarun Wadekar /******************************************************************************* 174*41612559SVarun Wadekar * GICv2 & interrupt handling related constants 175*41612559SVarun Wadekar ******************************************************************************/ 176*41612559SVarun Wadekar #define TEGRA_GICD_BASE 0x03881000 177*41612559SVarun Wadekar #define TEGRA_GICC_BASE 0x03882000 178*41612559SVarun Wadekar 179*41612559SVarun Wadekar /******************************************************************************* 180*41612559SVarun Wadekar * Security Engine related constants 181*41612559SVarun Wadekar ******************************************************************************/ 182*41612559SVarun Wadekar #define TEGRA_SE0_BASE 0x03AC0000 183*41612559SVarun Wadekar #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C 184*41612559SVarun Wadekar #define TEGRA_PKA1_BASE 0x03AD0000 185*41612559SVarun Wadekar #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 186*41612559SVarun Wadekar #define TEGRA_RNG1_BASE 0x03AE0000 187*41612559SVarun Wadekar #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 188*41612559SVarun Wadekar 189*41612559SVarun Wadekar /******************************************************************************* 190*41612559SVarun Wadekar * Tegra micro-seconds timer constants 191*41612559SVarun Wadekar ******************************************************************************/ 192*41612559SVarun Wadekar #define TEGRA_TMRUS_BASE 0x0C2E0000 193*41612559SVarun Wadekar 194*41612559SVarun Wadekar /******************************************************************************* 195*41612559SVarun Wadekar * Tegra Power Mgmt Controller constants 196*41612559SVarun Wadekar ******************************************************************************/ 197*41612559SVarun Wadekar #define TEGRA_PMC_BASE 0x0C360000 198*41612559SVarun Wadekar 199*41612559SVarun Wadekar /******************************************************************************* 200*41612559SVarun Wadekar * Tegra scratch registers constants 201*41612559SVarun Wadekar ******************************************************************************/ 202*41612559SVarun Wadekar #define TEGRA_SCRATCH_BASE 0x0C390000 203*41612559SVarun Wadekar #define SECURE_SCRATCH_RSV1_LO 0x06C 204*41612559SVarun Wadekar #define SECURE_SCRATCH_RSV1_HI 0x070 205*41612559SVarun Wadekar #define SECURE_SCRATCH_RSV6 0x094 206*41612559SVarun Wadekar #define SECURE_SCRATCH_RSV11_LO 0x0BC 207*41612559SVarun Wadekar #define SECURE_SCRATCH_RSV11_HI 0x0C0 208*41612559SVarun Wadekar #define SECURE_SCRATCH_RSV53_LO 0x20C 209*41612559SVarun Wadekar #define SECURE_SCRATCH_RSV53_HI 0x210 210*41612559SVarun Wadekar #define SECURE_SCRATCH_RSV54_HI 0x218 211*41612559SVarun Wadekar #define SECURE_SCRATCH_RSV55_LO 0x21C 212*41612559SVarun Wadekar #define SECURE_SCRATCH_RSV55_HI 0x220 213*41612559SVarun Wadekar 214*41612559SVarun Wadekar /******************************************************************************* 215*41612559SVarun Wadekar * Tegra Memory Mapped Control Register Access Bus constants 216*41612559SVarun Wadekar ******************************************************************************/ 217*41612559SVarun Wadekar #define TEGRA_MMCRAB_BASE 0x0E000000 218*41612559SVarun Wadekar 219*41612559SVarun Wadekar /******************************************************************************* 220*41612559SVarun Wadekar * Tegra SMMU Controller constants 221*41612559SVarun Wadekar ******************************************************************************/ 222*41612559SVarun Wadekar #define TEGRA_SMMU_BASE 0x10000000 223*41612559SVarun Wadekar 224*41612559SVarun Wadekar /******************************************************************************* 225*41612559SVarun Wadekar * Tegra TZRAM constants 226*41612559SVarun Wadekar ******************************************************************************/ 227*41612559SVarun Wadekar #define TEGRA_TZRAM_BASE 0x40000000 228*41612559SVarun Wadekar #define TEGRA_TZRAM_SIZE 0x40000 229*41612559SVarun Wadekar 230*41612559SVarun Wadekar /******************************************************************************* 231*41612559SVarun Wadekar * Tegra Clock and Reset Controller constants 232*41612559SVarun Wadekar ******************************************************************************/ 233*41612559SVarun Wadekar #define TEGRA_CAR_RESET_BASE 0x200000000 234*41612559SVarun Wadekar 235*41612559SVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 236