141612559SVarun Wadekar /* 241612559SVarun Wadekar * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 341612559SVarun Wadekar * 441612559SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 541612559SVarun Wadekar */ 641612559SVarun Wadekar 741612559SVarun Wadekar #ifndef __TEGRA_DEF_H__ 841612559SVarun Wadekar #define __TEGRA_DEF_H__ 941612559SVarun Wadekar 1041612559SVarun Wadekar #include <lib/utils_def.h> 1141612559SVarun Wadekar 1241612559SVarun Wadekar /******************************************************************************* 1341612559SVarun Wadekar * These values are used by the PSCI implementation during the `CPU_SUSPEND` 1441612559SVarun Wadekar * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 1541612559SVarun Wadekar * parameter. 1641612559SVarun Wadekar ******************************************************************************/ 1741612559SVarun Wadekar #define PSTATE_ID_CORE_IDLE 6 1841612559SVarun Wadekar #define PSTATE_ID_CORE_POWERDN 7 1941612559SVarun Wadekar #define PSTATE_ID_SOC_POWERDN 2 2041612559SVarun Wadekar 2141612559SVarun Wadekar /******************************************************************************* 2241612559SVarun Wadekar * Platform power states (used by PSCI framework) 2341612559SVarun Wadekar * 2441612559SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 2541612559SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 2641612559SVarun Wadekar ******************************************************************************/ 2741612559SVarun Wadekar #define PLAT_MAX_RET_STATE 1 2841612559SVarun Wadekar #define PLAT_MAX_OFF_STATE 8 2941612559SVarun Wadekar 3041612559SVarun Wadekar /******************************************************************************* 3141612559SVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 3241612559SVarun Wadekar ******************************************************************************/ 3341612559SVarun Wadekar #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 3441612559SVarun Wadekar #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 3541612559SVarun Wadekar #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 3641612559SVarun Wadekar #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 3741612559SVarun Wadekar #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 3841612559SVarun Wadekar #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 3941612559SVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 4041612559SVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 4141612559SVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 4241612559SVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 4341612559SVarun Wadekar 4441612559SVarun Wadekar /******************************************************************************* 4541612559SVarun Wadekar * Secure IRQ definitions 4641612559SVarun Wadekar ******************************************************************************/ 4741612559SVarun Wadekar #define TEGRA186_MAX_SEC_IRQS 5 4841612559SVarun Wadekar #define TEGRA186_BPMP_WDT_IRQ 46 4941612559SVarun Wadekar #define TEGRA186_SPE_WDT_IRQ 47 5041612559SVarun Wadekar #define TEGRA186_SCE_WDT_IRQ 48 5141612559SVarun Wadekar #define TEGRA186_TOP_WDT_IRQ 49 5241612559SVarun Wadekar #define TEGRA186_AON_WDT_IRQ 50 5341612559SVarun Wadekar 5441612559SVarun Wadekar #define TEGRA186_SEC_IRQ_TARGET_MASK 0xFF /* 8 Carmel */ 5541612559SVarun Wadekar 5641612559SVarun Wadekar /******************************************************************************* 5741612559SVarun Wadekar * Tegra Miscellanous register constants 5841612559SVarun Wadekar ******************************************************************************/ 5941612559SVarun Wadekar #define TEGRA_MISC_BASE 0x00100000 6041612559SVarun Wadekar #define HARDWARE_REVISION_OFFSET 0x4 6141612559SVarun Wadekar 6241612559SVarun Wadekar #define MISCREG_PFCFG 0x200C 6341612559SVarun Wadekar 6441612559SVarun Wadekar /******************************************************************************* 6541612559SVarun Wadekar * Tegra TSA Controller constants 6641612559SVarun Wadekar ******************************************************************************/ 6741612559SVarun Wadekar #define TEGRA_TSA_BASE 0x02000000 6841612559SVarun Wadekar 6941612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SESWR 0x1010 7041612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 7141612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_ETRW 0xD034 7241612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 7341612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x3020 7441612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 7541612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AXISW 0x8008 7641612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 7741612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_HDAW 0xD008 7841612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x1100 7941612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xE018 8041612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 8141612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x9008 8241612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 8341612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9028 8441612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 8541612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xB008 8641612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 8741612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6008 8841612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 8941612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AFIW 0xF008 9041612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 9141612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SATAW 0x4008 9241612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 9341612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_EQOSW 0x3038 9441612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 9541612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x6018 9641612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 9741612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x6028 9841612559SVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 9941612559SVarun Wadekar 10041612559SVarun Wadekar #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) 10141612559SVarun Wadekar #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) 10241612559SVarun Wadekar 10341612559SVarun Wadekar /******************************************************************************* 10441612559SVarun Wadekar * Tegra Memory Controller constants 10541612559SVarun Wadekar ******************************************************************************/ 10641612559SVarun Wadekar #define TEGRA_MC_STREAMID_BASE 0x02C00000 10741612559SVarun Wadekar #define TEGRA_MC_BASE 0x02C10000 10841612559SVarun Wadekar 1093b2b3375SVarun Wadekar /* General Security Carveout register macros */ 1103b2b3375SVarun Wadekar #define MC_GSC_CONFIG_REGS_SIZE 0x40 1113b2b3375SVarun Wadekar #define MC_GSC_LOCK_CFG_SETTINGS_BIT (1 << 1) 1123b2b3375SVarun Wadekar #define MC_GSC_ENABLE_TZ_LOCK_BIT (1 << 0) 1133b2b3375SVarun Wadekar #define MC_GSC_SIZE_RANGE_4KB_SHIFT 27 1143b2b3375SVarun Wadekar #define MC_GSC_BASE_LO_SHIFT 12 1153b2b3375SVarun Wadekar #define MC_GSC_BASE_LO_MASK 0xFFFFF 1163b2b3375SVarun Wadekar #define MC_GSC_BASE_HI_SHIFT 0 1173b2b3375SVarun Wadekar #define MC_GSC_BASE_HI_MASK 3 1183b2b3375SVarun Wadekar 11941612559SVarun Wadekar /* TZDRAM carveout configuration registers */ 12041612559SVarun Wadekar #define MC_SECURITY_CFG0_0 0x70 12141612559SVarun Wadekar #define MC_SECURITY_CFG1_0 0x74 12241612559SVarun Wadekar #define MC_SECURITY_CFG3_0 0x9BC 12341612559SVarun Wadekar 12441612559SVarun Wadekar /* Video Memory carveout configuration registers */ 12541612559SVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI 0x978 12641612559SVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO 0x648 12741612559SVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 12841612559SVarun Wadekar 1293b2b3375SVarun Wadekar /* 1303b2b3375SVarun Wadekar * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the 1313b2b3375SVarun Wadekar * non-overlapping Video memory region 1323b2b3375SVarun Wadekar */ 1333b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0 1343b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4 1353b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8 1363b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC 1373b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0 1383b2b3375SVarun Wadekar 13941612559SVarun Wadekar /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 14041612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_CFG 0x2190 1413b2b3375SVarun Wadekar #define MC_TZRAM_BASE_LO 0x2194 1423b2b3375SVarun Wadekar #define MC_TZRAM_BASE_HI 0x2198 1433b2b3375SVarun Wadekar #define MC_TZRAM_SIZE 0x219C 1443b2b3375SVarun Wadekar #define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0 14541612559SVarun Wadekar 14641612559SVarun Wadekar /* Memory Controller Reset Control registers */ 14741612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1 << 27) 14841612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28) 14941612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29) 15041612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30) 15141612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (1 << 31) 15241612559SVarun Wadekar 15341612559SVarun Wadekar /******************************************************************************* 15441612559SVarun Wadekar * Tegra UART Controller constants 15541612559SVarun Wadekar ******************************************************************************/ 15641612559SVarun Wadekar #define TEGRA_UARTA_BASE 0x03100000 15741612559SVarun Wadekar #define TEGRA_UARTB_BASE 0x03110000 15841612559SVarun Wadekar #define TEGRA_UARTC_BASE 0x0C280000 15941612559SVarun Wadekar #define TEGRA_UARTD_BASE 0x03130000 16041612559SVarun Wadekar #define TEGRA_UARTE_BASE 0x03140000 16141612559SVarun Wadekar #define TEGRA_UARTF_BASE 0x03150000 16241612559SVarun Wadekar #define TEGRA_UARTG_BASE 0x0C290000 16341612559SVarun Wadekar 16441612559SVarun Wadekar /******************************************************************************* 16541612559SVarun Wadekar * Tegra Fuse Controller related constants 16641612559SVarun Wadekar ******************************************************************************/ 16741612559SVarun Wadekar #define TEGRA_FUSE_BASE 0x03820000 16841612559SVarun Wadekar #define OPT_SUBREVISION 0x248 16941612559SVarun Wadekar #define SUBREVISION_MASK 0xF 17041612559SVarun Wadekar 17141612559SVarun Wadekar /******************************************************************************* 17241612559SVarun Wadekar * GICv2 & interrupt handling related constants 17341612559SVarun Wadekar ******************************************************************************/ 17441612559SVarun Wadekar #define TEGRA_GICD_BASE 0x03881000 17541612559SVarun Wadekar #define TEGRA_GICC_BASE 0x03882000 17641612559SVarun Wadekar 17741612559SVarun Wadekar /******************************************************************************* 17841612559SVarun Wadekar * Security Engine related constants 17941612559SVarun Wadekar ******************************************************************************/ 18041612559SVarun Wadekar #define TEGRA_SE0_BASE 0x03AC0000 18141612559SVarun Wadekar #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C 18241612559SVarun Wadekar #define TEGRA_PKA1_BASE 0x03AD0000 18341612559SVarun Wadekar #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 18441612559SVarun Wadekar #define TEGRA_RNG1_BASE 0x03AE0000 18541612559SVarun Wadekar #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 18641612559SVarun Wadekar 18741612559SVarun Wadekar /******************************************************************************* 18841612559SVarun Wadekar * Tegra micro-seconds timer constants 18941612559SVarun Wadekar ******************************************************************************/ 19041612559SVarun Wadekar #define TEGRA_TMRUS_BASE 0x0C2E0000 191d82f5a36SSteven Kao #define TEGRA_TMRUS_SIZE 0x10000 19241612559SVarun Wadekar 19341612559SVarun Wadekar /******************************************************************************* 19441612559SVarun Wadekar * Tegra Power Mgmt Controller constants 19541612559SVarun Wadekar ******************************************************************************/ 19641612559SVarun Wadekar #define TEGRA_PMC_BASE 0x0C360000 19741612559SVarun Wadekar 19841612559SVarun Wadekar /******************************************************************************* 19941612559SVarun Wadekar * Tegra scratch registers constants 20041612559SVarun Wadekar ******************************************************************************/ 20141612559SVarun Wadekar #define TEGRA_SCRATCH_BASE 0x0C390000 20241612559SVarun Wadekar #define SECURE_SCRATCH_RSV1_LO 0x06C 20341612559SVarun Wadekar #define SECURE_SCRATCH_RSV1_HI 0x070 20441612559SVarun Wadekar #define SECURE_SCRATCH_RSV6 0x094 20541612559SVarun Wadekar #define SECURE_SCRATCH_RSV11_LO 0x0BC 20641612559SVarun Wadekar #define SECURE_SCRATCH_RSV11_HI 0x0C0 20741612559SVarun Wadekar #define SECURE_SCRATCH_RSV53_LO 0x20C 20841612559SVarun Wadekar #define SECURE_SCRATCH_RSV53_HI 0x210 20941612559SVarun Wadekar #define SECURE_SCRATCH_RSV54_HI 0x218 21041612559SVarun Wadekar #define SECURE_SCRATCH_RSV55_LO 0x21C 21141612559SVarun Wadekar #define SECURE_SCRATCH_RSV55_HI 0x220 21241612559SVarun Wadekar 21341612559SVarun Wadekar /******************************************************************************* 21441612559SVarun Wadekar * Tegra Memory Mapped Control Register Access Bus constants 21541612559SVarun Wadekar ******************************************************************************/ 21641612559SVarun Wadekar #define TEGRA_MMCRAB_BASE 0x0E000000 21741612559SVarun Wadekar 21841612559SVarun Wadekar /******************************************************************************* 21941612559SVarun Wadekar * Tegra SMMU Controller constants 22041612559SVarun Wadekar ******************************************************************************/ 2210ea8881eSPritesh Raithatha #define TEGRA_SMMU0_BASE 0x12000000 2220ea8881eSPritesh Raithatha #define TEGRA_SMMU1_BASE 0x11000000 2230ea8881eSPritesh Raithatha #define TEGRA_SMMU2_BASE 0x10000000 22441612559SVarun Wadekar 22541612559SVarun Wadekar /******************************************************************************* 22641612559SVarun Wadekar * Tegra TZRAM constants 22741612559SVarun Wadekar ******************************************************************************/ 22841612559SVarun Wadekar #define TEGRA_TZRAM_BASE 0x40000000 22941612559SVarun Wadekar #define TEGRA_TZRAM_SIZE 0x40000 23041612559SVarun Wadekar 23141612559SVarun Wadekar /******************************************************************************* 23241612559SVarun Wadekar * Tegra Clock and Reset Controller constants 23341612559SVarun Wadekar ******************************************************************************/ 23441612559SVarun Wadekar #define TEGRA_CAR_RESET_BASE 0x200000000 235*2fdd9ae6SVarun Wadekar #define TEGRA_GPU_RESET_REG_OFFSET 0x18UL 236*2fdd9ae6SVarun Wadekar #define GPU_RESET_BIT (1UL << 0) 23741612559SVarun Wadekar 23841612559SVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 239