141612559SVarun Wadekar /* 241612559SVarun Wadekar * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 341612559SVarun Wadekar * 441612559SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 541612559SVarun Wadekar */ 641612559SVarun Wadekar 741612559SVarun Wadekar #ifndef __TEGRA_DEF_H__ 841612559SVarun Wadekar #define __TEGRA_DEF_H__ 941612559SVarun Wadekar 1041612559SVarun Wadekar #include <lib/utils_def.h> 1141612559SVarun Wadekar 1241612559SVarun Wadekar /******************************************************************************* 1341612559SVarun Wadekar * These values are used by the PSCI implementation during the `CPU_SUSPEND` 1441612559SVarun Wadekar * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 1541612559SVarun Wadekar * parameter. 1641612559SVarun Wadekar ******************************************************************************/ 1741612559SVarun Wadekar #define PSTATE_ID_CORE_IDLE 6 1841612559SVarun Wadekar #define PSTATE_ID_CORE_POWERDN 7 1941612559SVarun Wadekar #define PSTATE_ID_SOC_POWERDN 2 2041612559SVarun Wadekar 2141612559SVarun Wadekar /******************************************************************************* 2241612559SVarun Wadekar * Platform power states (used by PSCI framework) 2341612559SVarun Wadekar * 2441612559SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 2541612559SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 2641612559SVarun Wadekar ******************************************************************************/ 2741612559SVarun Wadekar #define PLAT_MAX_RET_STATE 1 2841612559SVarun Wadekar #define PLAT_MAX_OFF_STATE 8 2941612559SVarun Wadekar 3041612559SVarun Wadekar /******************************************************************************* 3141612559SVarun Wadekar * Secure IRQ definitions 3241612559SVarun Wadekar ******************************************************************************/ 3341612559SVarun Wadekar #define TEGRA186_MAX_SEC_IRQS 5 3441612559SVarun Wadekar #define TEGRA186_BPMP_WDT_IRQ 46 3541612559SVarun Wadekar #define TEGRA186_SPE_WDT_IRQ 47 3641612559SVarun Wadekar #define TEGRA186_SCE_WDT_IRQ 48 3741612559SVarun Wadekar #define TEGRA186_TOP_WDT_IRQ 49 3841612559SVarun Wadekar #define TEGRA186_AON_WDT_IRQ 50 3941612559SVarun Wadekar 4041612559SVarun Wadekar #define TEGRA186_SEC_IRQ_TARGET_MASK 0xFF /* 8 Carmel */ 4141612559SVarun Wadekar 4241612559SVarun Wadekar /******************************************************************************* 4341612559SVarun Wadekar * Tegra Miscellanous register constants 4441612559SVarun Wadekar ******************************************************************************/ 4513dcbc6fSSteven Kao #define TEGRA_MISC_BASE 0x00100000U 4641612559SVarun Wadekar 4713dcbc6fSSteven Kao #define HARDWARE_REVISION_OFFSET 0x4U 4813dcbc6fSSteven Kao #define MISCREG_EMU_REVID 0x3160U 4913dcbc6fSSteven Kao #define BOARD_MASK_BITS 0xFFU 5013dcbc6fSSteven Kao #define BOARD_SHIFT_BITS 24U 5113dcbc6fSSteven Kao #define MISCREG_PFCFG 0x200CU 5241612559SVarun Wadekar 5341612559SVarun Wadekar /******************************************************************************* 5441612559SVarun Wadekar * Tegra Memory Controller constants 5541612559SVarun Wadekar ******************************************************************************/ 5641612559SVarun Wadekar #define TEGRA_MC_STREAMID_BASE 0x02C00000 5741612559SVarun Wadekar #define TEGRA_MC_BASE 0x02C10000 5841612559SVarun Wadekar 593b2b3375SVarun Wadekar /* General Security Carveout register macros */ 603b2b3375SVarun Wadekar #define MC_GSC_CONFIG_REGS_SIZE 0x40 613b2b3375SVarun Wadekar #define MC_GSC_LOCK_CFG_SETTINGS_BIT (1 << 1) 623b2b3375SVarun Wadekar #define MC_GSC_ENABLE_TZ_LOCK_BIT (1 << 0) 633b2b3375SVarun Wadekar #define MC_GSC_SIZE_RANGE_4KB_SHIFT 27 643b2b3375SVarun Wadekar #define MC_GSC_BASE_LO_SHIFT 12 653b2b3375SVarun Wadekar #define MC_GSC_BASE_LO_MASK 0xFFFFF 663b2b3375SVarun Wadekar #define MC_GSC_BASE_HI_SHIFT 0 673b2b3375SVarun Wadekar #define MC_GSC_BASE_HI_MASK 3 68*1d9aad42SVarun Wadekar #define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31) 693b2b3375SVarun Wadekar 7041612559SVarun Wadekar /* TZDRAM carveout configuration registers */ 7141612559SVarun Wadekar #define MC_SECURITY_CFG0_0 0x70 7241612559SVarun Wadekar #define MC_SECURITY_CFG1_0 0x74 7341612559SVarun Wadekar #define MC_SECURITY_CFG3_0 0x9BC 7441612559SVarun Wadekar 75c0e1bcd0SHarvey Hsieh #define MC_SECURITY_BOM_MASK (U(0xFFF) << 20) 76c0e1bcd0SHarvey Hsieh #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) 77c0e1bcd0SHarvey Hsieh #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) 78c0e1bcd0SHarvey Hsieh 7941612559SVarun Wadekar /* Video Memory carveout configuration registers */ 8041612559SVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI 0x978 8141612559SVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO 0x648 8241612559SVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 8341612559SVarun Wadekar 843b2b3375SVarun Wadekar /* 853b2b3375SVarun Wadekar * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the 863b2b3375SVarun Wadekar * non-overlapping Video memory region 873b2b3375SVarun Wadekar */ 883b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0 893b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4 903b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8 913b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC 923b2b3375SVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0 933b2b3375SVarun Wadekar 9441612559SVarun Wadekar /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 9541612559SVarun Wadekar #define MC_TZRAM_CARVEOUT_CFG 0x2190 963b2b3375SVarun Wadekar #define MC_TZRAM_BASE_LO 0x2194 973b2b3375SVarun Wadekar #define MC_TZRAM_BASE_HI 0x2198 983b2b3375SVarun Wadekar #define MC_TZRAM_SIZE 0x219C 99*1d9aad42SVarun Wadekar #define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0) 100*1d9aad42SVarun Wadekar #define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4) 101*1d9aad42SVarun Wadekar #define TZRAM_ALLOW_MPCORER (U(1) << 7) 102*1d9aad42SVarun Wadekar #define TZRAM_ALLOW_MPCOREW (U(1) << 25) 10341612559SVarun Wadekar 10441612559SVarun Wadekar /* Memory Controller Reset Control registers */ 10541612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28) 10641612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29) 10741612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30) 10841612559SVarun Wadekar #define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (1 << 31) 10941612559SVarun Wadekar 11041612559SVarun Wadekar /******************************************************************************* 11141612559SVarun Wadekar * Tegra UART Controller constants 11241612559SVarun Wadekar ******************************************************************************/ 11341612559SVarun Wadekar #define TEGRA_UARTA_BASE 0x03100000 11441612559SVarun Wadekar #define TEGRA_UARTB_BASE 0x03110000 11541612559SVarun Wadekar #define TEGRA_UARTC_BASE 0x0C280000 11641612559SVarun Wadekar #define TEGRA_UARTD_BASE 0x03130000 11741612559SVarun Wadekar #define TEGRA_UARTE_BASE 0x03140000 11841612559SVarun Wadekar #define TEGRA_UARTF_BASE 0x03150000 11941612559SVarun Wadekar #define TEGRA_UARTG_BASE 0x0C290000 12041612559SVarun Wadekar 12141612559SVarun Wadekar /******************************************************************************* 12241612559SVarun Wadekar * Tegra Fuse Controller related constants 12341612559SVarun Wadekar ******************************************************************************/ 12441612559SVarun Wadekar #define TEGRA_FUSE_BASE 0x03820000 12541612559SVarun Wadekar #define OPT_SUBREVISION 0x248 12641612559SVarun Wadekar #define SUBREVISION_MASK 0xF 12741612559SVarun Wadekar 12841612559SVarun Wadekar /******************************************************************************* 12941612559SVarun Wadekar * GICv2 & interrupt handling related constants 13041612559SVarun Wadekar ******************************************************************************/ 13141612559SVarun Wadekar #define TEGRA_GICD_BASE 0x03881000 13241612559SVarun Wadekar #define TEGRA_GICC_BASE 0x03882000 13341612559SVarun Wadekar 13441612559SVarun Wadekar /******************************************************************************* 13541612559SVarun Wadekar * Security Engine related constants 13641612559SVarun Wadekar ******************************************************************************/ 13741612559SVarun Wadekar #define TEGRA_SE0_BASE 0x03AC0000 13841612559SVarun Wadekar #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C 13941612559SVarun Wadekar #define TEGRA_PKA1_BASE 0x03AD0000 14041612559SVarun Wadekar #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 14141612559SVarun Wadekar #define TEGRA_RNG1_BASE 0x03AE0000 14241612559SVarun Wadekar #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 14341612559SVarun Wadekar 14441612559SVarun Wadekar /******************************************************************************* 14541612559SVarun Wadekar * Tegra micro-seconds timer constants 14641612559SVarun Wadekar ******************************************************************************/ 14741612559SVarun Wadekar #define TEGRA_TMRUS_BASE 0x0C2E0000 148d82f5a36SSteven Kao #define TEGRA_TMRUS_SIZE 0x10000 14941612559SVarun Wadekar 15041612559SVarun Wadekar /******************************************************************************* 15141612559SVarun Wadekar * Tegra Power Mgmt Controller constants 15241612559SVarun Wadekar ******************************************************************************/ 15341612559SVarun Wadekar #define TEGRA_PMC_BASE 0x0C360000 15441612559SVarun Wadekar 15541612559SVarun Wadekar /******************************************************************************* 15641612559SVarun Wadekar * Tegra scratch registers constants 15741612559SVarun Wadekar ******************************************************************************/ 15841612559SVarun Wadekar #define TEGRA_SCRATCH_BASE 0x0C390000 15941612559SVarun Wadekar #define SECURE_SCRATCH_RSV1_LO 0x06C 16041612559SVarun Wadekar #define SECURE_SCRATCH_RSV1_HI 0x070 16141612559SVarun Wadekar #define SECURE_SCRATCH_RSV6 0x094 16241612559SVarun Wadekar #define SECURE_SCRATCH_RSV11_LO 0x0BC 16341612559SVarun Wadekar #define SECURE_SCRATCH_RSV11_HI 0x0C0 16441612559SVarun Wadekar #define SECURE_SCRATCH_RSV53_LO 0x20C 16541612559SVarun Wadekar #define SECURE_SCRATCH_RSV53_HI 0x210 16641612559SVarun Wadekar #define SECURE_SCRATCH_RSV54_HI 0x218 16741612559SVarun Wadekar #define SECURE_SCRATCH_RSV55_LO 0x21C 16841612559SVarun Wadekar #define SECURE_SCRATCH_RSV55_HI 0x220 16941612559SVarun Wadekar 17041612559SVarun Wadekar /******************************************************************************* 17141612559SVarun Wadekar * Tegra Memory Mapped Control Register Access Bus constants 17241612559SVarun Wadekar ******************************************************************************/ 17341612559SVarun Wadekar #define TEGRA_MMCRAB_BASE 0x0E000000 17441612559SVarun Wadekar 17541612559SVarun Wadekar /******************************************************************************* 17641612559SVarun Wadekar * Tegra SMMU Controller constants 17741612559SVarun Wadekar ******************************************************************************/ 1780ea8881eSPritesh Raithatha #define TEGRA_SMMU0_BASE 0x12000000 1790ea8881eSPritesh Raithatha #define TEGRA_SMMU1_BASE 0x11000000 1800ea8881eSPritesh Raithatha #define TEGRA_SMMU2_BASE 0x10000000 18141612559SVarun Wadekar 18241612559SVarun Wadekar /******************************************************************************* 18341612559SVarun Wadekar * Tegra TZRAM constants 18441612559SVarun Wadekar ******************************************************************************/ 18541612559SVarun Wadekar #define TEGRA_TZRAM_BASE 0x40000000 18641612559SVarun Wadekar #define TEGRA_TZRAM_SIZE 0x40000 18741612559SVarun Wadekar 18841612559SVarun Wadekar /******************************************************************************* 18941612559SVarun Wadekar * Tegra Clock and Reset Controller constants 19041612559SVarun Wadekar ******************************************************************************/ 191c1485edfSSteven Kao #define TEGRA_CAR_RESET_BASE 0x20000000 1922fdd9ae6SVarun Wadekar #define TEGRA_GPU_RESET_REG_OFFSET 0x18UL 1932fdd9ae6SVarun Wadekar #define GPU_RESET_BIT (1UL << 0) 19441612559SVarun Wadekar 195719fdb6eSVarun Wadekar /******************************************************************************* 196bc019041SAjay Gupta * XUSB PADCTL 197bc019041SAjay Gupta ******************************************************************************/ 198bc019041SAjay Gupta #define TEGRA_XUSB_PADCTL_BASE (0x3520000U) 199bc019041SAjay Gupta #define TEGRA_XUSB_PADCTL_SIZE (0x10000U) 200bc019041SAjay Gupta #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) 201bc019041SAjay Gupta #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) 202bc019041SAjay Gupta #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) 203bc019041SAjay Gupta #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) 204bc019041SAjay Gupta #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) 205bc019041SAjay Gupta #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) 206bc019041SAjay Gupta 207bc019041SAjay Gupta /******************************************************************************* 208bc019041SAjay Gupta * XUSB STREAMIDs 209bc019041SAjay Gupta ******************************************************************************/ 210bc019041SAjay Gupta #define TEGRA_SID_XUSB_HOST (0x1bU) 211bc019041SAjay Gupta #define TEGRA_SID_XUSB_DEV (0x1cU) 212bc019041SAjay Gupta #define TEGRA_SID_XUSB_VF0 (0x5dU) 213bc019041SAjay Gupta #define TEGRA_SID_XUSB_VF1 (0x5eU) 214bc019041SAjay Gupta #define TEGRA_SID_XUSB_VF2 (0x5fU) 215bc019041SAjay Gupta #define TEGRA_SID_XUSB_VF3 (0x60U) 216bc019041SAjay Gupta 21741612559SVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 218