1*653fc380SVarun Wadekar /* 2*653fc380SVarun Wadekar * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3*653fc380SVarun Wadekar * 4*653fc380SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5*653fc380SVarun Wadekar */ 6*653fc380SVarun Wadekar 7*653fc380SVarun Wadekar #ifndef __TEGRA194_PRIVATE_H__ 8*653fc380SVarun Wadekar #define __TEGRA194_PRIVATE_H__ 9*653fc380SVarun Wadekar 10*653fc380SVarun Wadekar void tegra194_cpu_reset_handler(void); 11*653fc380SVarun Wadekar uint64_t tegra194_get_cpu_reset_handler_base(void); 12*653fc380SVarun Wadekar uint64_t tegra194_get_cpu_reset_handler_size(void); 13*653fc380SVarun Wadekar uint64_t tegra194_get_smmu_ctx_offset(void); 14*653fc380SVarun Wadekar 15*653fc380SVarun Wadekar #endif /* __TEGRA194_PRIVATE_H__ */ 16