13cf3183fSVarun Wadekar /* 250cd8646SVarun Wadekar * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 43cf3183fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 53cf3183fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 63cf3183fSVarun Wadekar * 73cf3183fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 83cf3183fSVarun Wadekar * list of conditions and the following disclaimer. 93cf3183fSVarun Wadekar * 103cf3183fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 113cf3183fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 123cf3183fSVarun Wadekar * and/or other materials provided with the distribution. 133cf3183fSVarun Wadekar * 143cf3183fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 153cf3183fSVarun Wadekar * to endorse or promote products derived from this software without specific 163cf3183fSVarun Wadekar * prior written permission. 173cf3183fSVarun Wadekar * 183cf3183fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 193cf3183fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 203cf3183fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 213cf3183fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 223cf3183fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 233cf3183fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 243cf3183fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 253cf3183fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 263cf3183fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 273cf3183fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 283cf3183fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 293cf3183fSVarun Wadekar */ 303cf3183fSVarun Wadekar 313cf3183fSVarun Wadekar #ifndef __TEGRA_DEF_H__ 323cf3183fSVarun Wadekar #define __TEGRA_DEF_H__ 333cf3183fSVarun Wadekar 343cf3183fSVarun Wadekar /******************************************************************************* 35*dec349c8SVarun Wadekar * MCE apertures used by the ARI interface 36*dec349c8SVarun Wadekar * 37*dec349c8SVarun Wadekar * Aperture 0 - Cpu0 (ARM Cortex A-57) 38*dec349c8SVarun Wadekar * Aperture 1 - Cpu1 (ARM Cortex A-57) 39*dec349c8SVarun Wadekar * Aperture 2 - Cpu2 (ARM Cortex A-57) 40*dec349c8SVarun Wadekar * Aperture 3 - Cpu3 (ARM Cortex A-57) 41*dec349c8SVarun Wadekar * Aperture 4 - Cpu4 (Denver15) 42*dec349c8SVarun Wadekar * Aperture 5 - Cpu5 (Denver15) 43*dec349c8SVarun Wadekar ******************************************************************************/ 44*dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_0_OFFSET 0x0 45*dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_1_OFFSET 0x10000 46*dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_2_OFFSET 0x20000 47*dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_3_OFFSET 0x30000 48*dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_4_OFFSET 0x40000 49*dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_5_OFFSET 0x50000 50*dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET 51*dec349c8SVarun Wadekar 52*dec349c8SVarun Wadekar /* number of apertures */ 53*dec349c8SVarun Wadekar #define MCE_ARI_APERTURES_MAX 6 54*dec349c8SVarun Wadekar 55*dec349c8SVarun Wadekar /* each ARI aperture is 64KB */ 56*dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_SIZE 0x10000 57*dec349c8SVarun Wadekar 58*dec349c8SVarun Wadekar /******************************************************************************* 59*dec349c8SVarun Wadekar * CPU core id macros for the MCE_ONLINE_CORE ARI 60*dec349c8SVarun Wadekar ******************************************************************************/ 61*dec349c8SVarun Wadekar #define MCE_CORE_ID_MAX 8 62*dec349c8SVarun Wadekar #define MCE_CORE_ID_MASK 0x7 63*dec349c8SVarun Wadekar 64*dec349c8SVarun Wadekar /******************************************************************************* 657afd4637SVarun Wadekar * These values are used by the PSCI implementation during the `CPU_SUSPEND` 667afd4637SVarun Wadekar * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 677afd4637SVarun Wadekar * parameter. 683cf3183fSVarun Wadekar ******************************************************************************/ 697afd4637SVarun Wadekar #define PSTATE_ID_CORE_IDLE 6 707afd4637SVarun Wadekar #define PSTATE_ID_CORE_POWERDN 7 717afd4637SVarun Wadekar #define PSTATE_ID_SOC_POWERDN 2 727afd4637SVarun Wadekar 737afd4637SVarun Wadekar /******************************************************************************* 747afd4637SVarun Wadekar * Platform power states (used by PSCI framework) 757afd4637SVarun Wadekar * 767afd4637SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 777afd4637SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 787afd4637SVarun Wadekar ******************************************************************************/ 797afd4637SVarun Wadekar #define PLAT_MAX_RET_STATE 1 807afd4637SVarun Wadekar #define PLAT_MAX_OFF_STATE 8 813cf3183fSVarun Wadekar 823cf3183fSVarun Wadekar /******************************************************************************* 833cf3183fSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 843cf3183fSVarun Wadekar ******************************************************************************/ 853cf3183fSVarun Wadekar #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 863cf3183fSVarun Wadekar #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 873cf3183fSVarun Wadekar #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 883cf3183fSVarun Wadekar #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 893cf3183fSVarun Wadekar #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 903cf3183fSVarun Wadekar #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 913cf3183fSVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 923cf3183fSVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 933cf3183fSVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 943cf3183fSVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 953cf3183fSVarun Wadekar 963cf3183fSVarun Wadekar /******************************************************************************* 9750cd8646SVarun Wadekar * Secure IRQ definitions 9850cd8646SVarun Wadekar ******************************************************************************/ 9950cd8646SVarun Wadekar #define TEGRA186_TOP_WDT_IRQ 49 10050cd8646SVarun Wadekar #define TEGRA186_AON_WDT_IRQ 50 10150cd8646SVarun Wadekar 10250cd8646SVarun Wadekar #define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */ 10350cd8646SVarun Wadekar 10450cd8646SVarun Wadekar /******************************************************************************* 1053cf3183fSVarun Wadekar * Tegra Miscellanous register constants 1063cf3183fSVarun Wadekar ******************************************************************************/ 1073cf3183fSVarun Wadekar #define TEGRA_MISC_BASE 0x00100000 108be87d920SVarun Wadekar #define HARDWARE_REVISION_OFFSET 0x4 109abd3a91dSVarun Wadekar 11050402b17SVarun Wadekar #define MISCREG_PFCFG 0x200C 1113cf3183fSVarun Wadekar 1123cf3183fSVarun Wadekar /******************************************************************************* 113e64ce3abSVarun Wadekar * Tegra TSA Controller constants 114e64ce3abSVarun Wadekar ******************************************************************************/ 115e64ce3abSVarun Wadekar #define TEGRA_TSA_BASE 0x02400000 116e64ce3abSVarun Wadekar 117e64ce3abSVarun Wadekar /******************************************************************************* 1183cf3183fSVarun Wadekar * Tegra Memory Controller constants 1193cf3183fSVarun Wadekar ******************************************************************************/ 1203cf3183fSVarun Wadekar #define TEGRA_MC_STREAMID_BASE 0x02C00000 1213cf3183fSVarun Wadekar #define TEGRA_MC_BASE 0x02C10000 1223cf3183fSVarun Wadekar 1233cf3183fSVarun Wadekar /******************************************************************************* 1243cf3183fSVarun Wadekar * Tegra UART Controller constants 1253cf3183fSVarun Wadekar ******************************************************************************/ 1263cf3183fSVarun Wadekar #define TEGRA_UARTA_BASE 0x03100000 1273cf3183fSVarun Wadekar #define TEGRA_UARTB_BASE 0x03110000 1283cf3183fSVarun Wadekar #define TEGRA_UARTC_BASE 0x0C280000 1293cf3183fSVarun Wadekar #define TEGRA_UARTD_BASE 0x03130000 1303cf3183fSVarun Wadekar #define TEGRA_UARTE_BASE 0x03140000 1313cf3183fSVarun Wadekar #define TEGRA_UARTF_BASE 0x03150000 1323cf3183fSVarun Wadekar #define TEGRA_UARTG_BASE 0x0C290000 1333cf3183fSVarun Wadekar 1343cf3183fSVarun Wadekar /******************************************************************************* 1351eed3838SVarun Wadekar * Tegra Fuse Controller related constants 1361eed3838SVarun Wadekar ******************************************************************************/ 1371eed3838SVarun Wadekar #define TEGRA_FUSE_BASE 0x03820000 1381eed3838SVarun Wadekar #define OPT_SUBREVISION 0x248 1391eed3838SVarun Wadekar #define SUBREVISION_MASK 0xFF 1401eed3838SVarun Wadekar 1411eed3838SVarun Wadekar /******************************************************************************* 1423cf3183fSVarun Wadekar * GICv2 & interrupt handling related constants 1433cf3183fSVarun Wadekar ******************************************************************************/ 1443cf3183fSVarun Wadekar #define TEGRA_GICD_BASE 0x03881000 1453cf3183fSVarun Wadekar #define TEGRA_GICC_BASE 0x03882000 1463cf3183fSVarun Wadekar 1473cf3183fSVarun Wadekar /******************************************************************************* 14850402b17SVarun Wadekar * Security Engine related constants 14950402b17SVarun Wadekar ******************************************************************************/ 15050402b17SVarun Wadekar #define TEGRA_SE0_BASE 0x03AC0000 15150402b17SVarun Wadekar #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C 15250402b17SVarun Wadekar #define TEGRA_PKA1_BASE 0x03AD0000 15350402b17SVarun Wadekar #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 15450402b17SVarun Wadekar #define TEGRA_RNG1_BASE 0x03AE0000 15550402b17SVarun Wadekar #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 15650402b17SVarun Wadekar 15750402b17SVarun Wadekar /******************************************************************************* 1583cf3183fSVarun Wadekar * Tegra Clock and Reset Controller constants 1593cf3183fSVarun Wadekar ******************************************************************************/ 1603cf3183fSVarun Wadekar #define TEGRA_CAR_RESET_BASE 0x05000000 1613cf3183fSVarun Wadekar 1623cf3183fSVarun Wadekar /******************************************************************************* 1633cf3183fSVarun Wadekar * Tegra micro-seconds timer constants 1643cf3183fSVarun Wadekar ******************************************************************************/ 1653cf3183fSVarun Wadekar #define TEGRA_TMRUS_BASE 0x0C2E0000 1663cf3183fSVarun Wadekar 1673cf3183fSVarun Wadekar /******************************************************************************* 1683cf3183fSVarun Wadekar * Tegra Power Mgmt Controller constants 1693cf3183fSVarun Wadekar ******************************************************************************/ 1703cf3183fSVarun Wadekar #define TEGRA_PMC_BASE 0x0C360000 1713cf3183fSVarun Wadekar 1723cf3183fSVarun Wadekar /******************************************************************************* 1733cf3183fSVarun Wadekar * Tegra scratch registers constants 1743cf3183fSVarun Wadekar ******************************************************************************/ 1753cf3183fSVarun Wadekar #define TEGRA_SCRATCH_BASE 0x0C390000 17650402b17SVarun Wadekar #define SECURE_SCRATCH_RSV6 0x680 17750402b17SVarun Wadekar #define SECURE_SCRATCH_RSV11_LO 0x6A8 17850402b17SVarun Wadekar #define SECURE_SCRATCH_RSV11_HI 0x6AC 17948afb167SVarun Wadekar #define SECURE_SCRATCH_RSV53_LO 0x7F8 18048afb167SVarun Wadekar #define SECURE_SCRATCH_RSV53_HI 0x7FC 181719f3ec2SHarvey Hsieh #define SECURE_SCRATCH_RSV54_HI 0x804 182719f3ec2SHarvey Hsieh #define SECURE_SCRATCH_RSV55_LO 0x808 183719f3ec2SHarvey Hsieh #define SECURE_SCRATCH_RSV55_HI 0x80C 1843cf3183fSVarun Wadekar 1853cf3183fSVarun Wadekar /******************************************************************************* 1863cf3183fSVarun Wadekar * Tegra Memory Mapped Control Register Access Bus constants 1873cf3183fSVarun Wadekar ******************************************************************************/ 1883cf3183fSVarun Wadekar #define TEGRA_MMCRAB_BASE 0x0E000000 1893cf3183fSVarun Wadekar 1903cf3183fSVarun Wadekar /******************************************************************************* 1913cf3183fSVarun Wadekar * Tegra SMMU Controller constants 1923cf3183fSVarun Wadekar ******************************************************************************/ 1933cf3183fSVarun Wadekar #define TEGRA_SMMU_BASE 0x12000000 1943cf3183fSVarun Wadekar 195d48c0c45SVarun Wadekar /******************************************************************************* 196d48c0c45SVarun Wadekar * Tegra TZRAM constants 197d48c0c45SVarun Wadekar ******************************************************************************/ 198d48c0c45SVarun Wadekar #define TEGRA_TZRAM_BASE 0x30000000 1992f583f8eSVarun Wadekar #define TEGRA_TZRAM_SIZE 0x40000 200d48c0c45SVarun Wadekar 2013cf3183fSVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 202