13cf3183fSVarun Wadekar /* 2b67a7c7cSVarun Wadekar * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 43cf3183fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 53cf3183fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 63cf3183fSVarun Wadekar * 73cf3183fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 83cf3183fSVarun Wadekar * list of conditions and the following disclaimer. 93cf3183fSVarun Wadekar * 103cf3183fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 113cf3183fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 123cf3183fSVarun Wadekar * and/or other materials provided with the distribution. 133cf3183fSVarun Wadekar * 143cf3183fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 153cf3183fSVarun Wadekar * to endorse or promote products derived from this software without specific 163cf3183fSVarun Wadekar * prior written permission. 173cf3183fSVarun Wadekar * 183cf3183fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 193cf3183fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 203cf3183fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 213cf3183fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 223cf3183fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 233cf3183fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 243cf3183fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 253cf3183fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 263cf3183fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 273cf3183fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 283cf3183fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 293cf3183fSVarun Wadekar */ 303cf3183fSVarun Wadekar 313cf3183fSVarun Wadekar #ifndef __TEGRA_DEF_H__ 323cf3183fSVarun Wadekar #define __TEGRA_DEF_H__ 333cf3183fSVarun Wadekar 343cf3183fSVarun Wadekar #include <platform_def.h> 353cf3183fSVarun Wadekar 363cf3183fSVarun Wadekar /******************************************************************************* 373cf3183fSVarun Wadekar * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 383cf3183fSVarun Wadekar * call as the `state-id` field in the 'power state' parameter. 393cf3183fSVarun Wadekar ******************************************************************************/ 40b67a7c7cSVarun Wadekar #define PSTATE_ID_SOC_POWERDN 1 413cf3183fSVarun Wadekar 423cf3183fSVarun Wadekar /******************************************************************************* 433cf3183fSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 443cf3183fSVarun Wadekar ******************************************************************************/ 453cf3183fSVarun Wadekar #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 463cf3183fSVarun Wadekar #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 473cf3183fSVarun Wadekar #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 483cf3183fSVarun Wadekar #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 493cf3183fSVarun Wadekar #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 503cf3183fSVarun Wadekar #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 513cf3183fSVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 523cf3183fSVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 533cf3183fSVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 543cf3183fSVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 553cf3183fSVarun Wadekar 563cf3183fSVarun Wadekar /******************************************************************************* 573cf3183fSVarun Wadekar * Tegra Miscellanous register constants 583cf3183fSVarun Wadekar ******************************************************************************/ 593cf3183fSVarun Wadekar #define TEGRA_MISC_BASE 0x00100000 603cf3183fSVarun Wadekar 613cf3183fSVarun Wadekar /******************************************************************************* 623cf3183fSVarun Wadekar * Tegra Memory Controller constants 633cf3183fSVarun Wadekar ******************************************************************************/ 643cf3183fSVarun Wadekar #define TEGRA_MC_STREAMID_BASE 0x02C00000 653cf3183fSVarun Wadekar #define TEGRA_MC_BASE 0x02C10000 663cf3183fSVarun Wadekar 673cf3183fSVarun Wadekar /******************************************************************************* 683cf3183fSVarun Wadekar * Tegra UART Controller constants 693cf3183fSVarun Wadekar ******************************************************************************/ 703cf3183fSVarun Wadekar #define TEGRA_UARTA_BASE 0x03100000 713cf3183fSVarun Wadekar #define TEGRA_UARTB_BASE 0x03110000 723cf3183fSVarun Wadekar #define TEGRA_UARTC_BASE 0x0C280000 733cf3183fSVarun Wadekar #define TEGRA_UARTD_BASE 0x03130000 743cf3183fSVarun Wadekar #define TEGRA_UARTE_BASE 0x03140000 753cf3183fSVarun Wadekar #define TEGRA_UARTF_BASE 0x03150000 763cf3183fSVarun Wadekar #define TEGRA_UARTG_BASE 0x0C290000 773cf3183fSVarun Wadekar 783cf3183fSVarun Wadekar /******************************************************************************* 793cf3183fSVarun Wadekar * GICv2 & interrupt handling related constants 803cf3183fSVarun Wadekar ******************************************************************************/ 813cf3183fSVarun Wadekar #define TEGRA_GICD_BASE 0x03881000 823cf3183fSVarun Wadekar #define TEGRA_GICC_BASE 0x03882000 833cf3183fSVarun Wadekar 843cf3183fSVarun Wadekar /******************************************************************************* 853cf3183fSVarun Wadekar * Tegra Clock and Reset Controller constants 863cf3183fSVarun Wadekar ******************************************************************************/ 873cf3183fSVarun Wadekar #define TEGRA_CAR_RESET_BASE 0x05000000 883cf3183fSVarun Wadekar 893cf3183fSVarun Wadekar /******************************************************************************* 903cf3183fSVarun Wadekar * Tegra micro-seconds timer constants 913cf3183fSVarun Wadekar ******************************************************************************/ 923cf3183fSVarun Wadekar #define TEGRA_TMRUS_BASE 0x0C2E0000 933cf3183fSVarun Wadekar 943cf3183fSVarun Wadekar /******************************************************************************* 953cf3183fSVarun Wadekar * Tegra Power Mgmt Controller constants 963cf3183fSVarun Wadekar ******************************************************************************/ 973cf3183fSVarun Wadekar #define TEGRA_PMC_BASE 0x0C360000 983cf3183fSVarun Wadekar 993cf3183fSVarun Wadekar /******************************************************************************* 1003cf3183fSVarun Wadekar * Tegra scratch registers constants 1013cf3183fSVarun Wadekar ******************************************************************************/ 1023cf3183fSVarun Wadekar #define TEGRA_SCRATCH_BASE 0x0C390000 1033cf3183fSVarun Wadekar 1043cf3183fSVarun Wadekar /******************************************************************************* 1053cf3183fSVarun Wadekar * Tegra Memory Mapped Control Register Access Bus constants 1063cf3183fSVarun Wadekar ******************************************************************************/ 1073cf3183fSVarun Wadekar #define TEGRA_MMCRAB_BASE 0x0E000000 1083cf3183fSVarun Wadekar 1093cf3183fSVarun Wadekar /******************************************************************************* 1103cf3183fSVarun Wadekar * Tegra SMMU Controller constants 1113cf3183fSVarun Wadekar ******************************************************************************/ 1123cf3183fSVarun Wadekar #define TEGRA_SMMU_BASE 0x12000000 1133cf3183fSVarun Wadekar 114*d48c0c45SVarun Wadekar /******************************************************************************* 115*d48c0c45SVarun Wadekar * Tegra TZRAM constants 116*d48c0c45SVarun Wadekar ******************************************************************************/ 117*d48c0c45SVarun Wadekar #define TEGRA_TZRAM_BASE 0x30000000 118*d48c0c45SVarun Wadekar #define TEGRA_TZRAM_SIZE 0x50000 119*d48c0c45SVarun Wadekar 1203cf3183fSVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 121