13cf3183fSVarun Wadekar /* 250cd8646SVarun Wadekar * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 43cf3183fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 53cf3183fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 63cf3183fSVarun Wadekar * 73cf3183fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 83cf3183fSVarun Wadekar * list of conditions and the following disclaimer. 93cf3183fSVarun Wadekar * 103cf3183fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 113cf3183fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 123cf3183fSVarun Wadekar * and/or other materials provided with the distribution. 133cf3183fSVarun Wadekar * 143cf3183fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 153cf3183fSVarun Wadekar * to endorse or promote products derived from this software without specific 163cf3183fSVarun Wadekar * prior written permission. 173cf3183fSVarun Wadekar * 183cf3183fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 193cf3183fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 203cf3183fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 213cf3183fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 223cf3183fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 233cf3183fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 243cf3183fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 253cf3183fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 263cf3183fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 273cf3183fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 283cf3183fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 293cf3183fSVarun Wadekar */ 303cf3183fSVarun Wadekar 313cf3183fSVarun Wadekar #ifndef __TEGRA_DEF_H__ 323cf3183fSVarun Wadekar #define __TEGRA_DEF_H__ 333cf3183fSVarun Wadekar 343cf3183fSVarun Wadekar #include <platform_def.h> 353cf3183fSVarun Wadekar 363cf3183fSVarun Wadekar /******************************************************************************* 377afd4637SVarun Wadekar * These values are used by the PSCI implementation during the `CPU_SUSPEND` 387afd4637SVarun Wadekar * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 397afd4637SVarun Wadekar * parameter. 403cf3183fSVarun Wadekar ******************************************************************************/ 417afd4637SVarun Wadekar #define PSTATE_ID_CORE_IDLE 6 427afd4637SVarun Wadekar #define PSTATE_ID_CORE_POWERDN 7 437afd4637SVarun Wadekar #define PSTATE_ID_SOC_POWERDN 2 447afd4637SVarun Wadekar 457afd4637SVarun Wadekar /******************************************************************************* 467afd4637SVarun Wadekar * Platform power states (used by PSCI framework) 477afd4637SVarun Wadekar * 487afd4637SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 497afd4637SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 507afd4637SVarun Wadekar ******************************************************************************/ 517afd4637SVarun Wadekar #define PLAT_MAX_RET_STATE 1 527afd4637SVarun Wadekar #define PLAT_MAX_OFF_STATE 8 533cf3183fSVarun Wadekar 543cf3183fSVarun Wadekar /******************************************************************************* 553cf3183fSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 563cf3183fSVarun Wadekar ******************************************************************************/ 573cf3183fSVarun Wadekar #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 583cf3183fSVarun Wadekar #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 593cf3183fSVarun Wadekar #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 603cf3183fSVarun Wadekar #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 613cf3183fSVarun Wadekar #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 623cf3183fSVarun Wadekar #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 633cf3183fSVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 643cf3183fSVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 653cf3183fSVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 663cf3183fSVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 673cf3183fSVarun Wadekar 683cf3183fSVarun Wadekar /******************************************************************************* 6950cd8646SVarun Wadekar * Secure IRQ definitions 7050cd8646SVarun Wadekar ******************************************************************************/ 7150cd8646SVarun Wadekar #define TEGRA186_TOP_WDT_IRQ 49 7250cd8646SVarun Wadekar #define TEGRA186_AON_WDT_IRQ 50 7350cd8646SVarun Wadekar 7450cd8646SVarun Wadekar #define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */ 7550cd8646SVarun Wadekar 7650cd8646SVarun Wadekar /******************************************************************************* 773cf3183fSVarun Wadekar * Tegra Miscellanous register constants 783cf3183fSVarun Wadekar ******************************************************************************/ 793cf3183fSVarun Wadekar #define TEGRA_MISC_BASE 0x00100000 80be87d920SVarun Wadekar #define HARDWARE_REVISION_OFFSET 0x4 81*abd3a91dSVarun Wadekar #define MAJOR_VERSION_SHIFT 0x4 82*abd3a91dSVarun Wadekar #define MAJOR_VERSION_MASK 0xF 83*abd3a91dSVarun Wadekar #define MINOR_VERSION_SHIFT 0x10 84*abd3a91dSVarun Wadekar #define MINOR_VERSION_MASK 0xF 85*abd3a91dSVarun Wadekar 8650402b17SVarun Wadekar #define MISCREG_PFCFG 0x200C 873cf3183fSVarun Wadekar 883cf3183fSVarun Wadekar /******************************************************************************* 89e64ce3abSVarun Wadekar * Tegra TSA Controller constants 90e64ce3abSVarun Wadekar ******************************************************************************/ 91e64ce3abSVarun Wadekar #define TEGRA_TSA_BASE 0x02400000 92e64ce3abSVarun Wadekar 93e64ce3abSVarun Wadekar /******************************************************************************* 943cf3183fSVarun Wadekar * Tegra Memory Controller constants 953cf3183fSVarun Wadekar ******************************************************************************/ 963cf3183fSVarun Wadekar #define TEGRA_MC_STREAMID_BASE 0x02C00000 973cf3183fSVarun Wadekar #define TEGRA_MC_BASE 0x02C10000 983cf3183fSVarun Wadekar 993cf3183fSVarun Wadekar /******************************************************************************* 1003cf3183fSVarun Wadekar * Tegra UART Controller constants 1013cf3183fSVarun Wadekar ******************************************************************************/ 1023cf3183fSVarun Wadekar #define TEGRA_UARTA_BASE 0x03100000 1033cf3183fSVarun Wadekar #define TEGRA_UARTB_BASE 0x03110000 1043cf3183fSVarun Wadekar #define TEGRA_UARTC_BASE 0x0C280000 1053cf3183fSVarun Wadekar #define TEGRA_UARTD_BASE 0x03130000 1063cf3183fSVarun Wadekar #define TEGRA_UARTE_BASE 0x03140000 1073cf3183fSVarun Wadekar #define TEGRA_UARTF_BASE 0x03150000 1083cf3183fSVarun Wadekar #define TEGRA_UARTG_BASE 0x0C290000 1093cf3183fSVarun Wadekar 1103cf3183fSVarun Wadekar /******************************************************************************* 1113cf3183fSVarun Wadekar * GICv2 & interrupt handling related constants 1123cf3183fSVarun Wadekar ******************************************************************************/ 1133cf3183fSVarun Wadekar #define TEGRA_GICD_BASE 0x03881000 1143cf3183fSVarun Wadekar #define TEGRA_GICC_BASE 0x03882000 1153cf3183fSVarun Wadekar 1163cf3183fSVarun Wadekar /******************************************************************************* 11750402b17SVarun Wadekar * Security Engine related constants 11850402b17SVarun Wadekar ******************************************************************************/ 11950402b17SVarun Wadekar #define TEGRA_SE0_BASE 0x03AC0000 12050402b17SVarun Wadekar #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C 12150402b17SVarun Wadekar #define TEGRA_PKA1_BASE 0x03AD0000 12250402b17SVarun Wadekar #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 12350402b17SVarun Wadekar #define TEGRA_RNG1_BASE 0x03AE0000 12450402b17SVarun Wadekar #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 12550402b17SVarun Wadekar 12650402b17SVarun Wadekar /******************************************************************************* 1273cf3183fSVarun Wadekar * Tegra Clock and Reset Controller constants 1283cf3183fSVarun Wadekar ******************************************************************************/ 1293cf3183fSVarun Wadekar #define TEGRA_CAR_RESET_BASE 0x05000000 1303cf3183fSVarun Wadekar 1313cf3183fSVarun Wadekar /******************************************************************************* 1323cf3183fSVarun Wadekar * Tegra micro-seconds timer constants 1333cf3183fSVarun Wadekar ******************************************************************************/ 1343cf3183fSVarun Wadekar #define TEGRA_TMRUS_BASE 0x0C2E0000 1353cf3183fSVarun Wadekar 1363cf3183fSVarun Wadekar /******************************************************************************* 1373cf3183fSVarun Wadekar * Tegra Power Mgmt Controller constants 1383cf3183fSVarun Wadekar ******************************************************************************/ 1393cf3183fSVarun Wadekar #define TEGRA_PMC_BASE 0x0C360000 1403cf3183fSVarun Wadekar 1413cf3183fSVarun Wadekar /******************************************************************************* 1423cf3183fSVarun Wadekar * Tegra scratch registers constants 1433cf3183fSVarun Wadekar ******************************************************************************/ 1443cf3183fSVarun Wadekar #define TEGRA_SCRATCH_BASE 0x0C390000 14550402b17SVarun Wadekar #define SECURE_SCRATCH_RSV6 0x680 14650402b17SVarun Wadekar #define SECURE_SCRATCH_RSV11_LO 0x6A8 14750402b17SVarun Wadekar #define SECURE_SCRATCH_RSV11_HI 0x6AC 1483cf3183fSVarun Wadekar 1493cf3183fSVarun Wadekar /******************************************************************************* 1503cf3183fSVarun Wadekar * Tegra Memory Mapped Control Register Access Bus constants 1513cf3183fSVarun Wadekar ******************************************************************************/ 1523cf3183fSVarun Wadekar #define TEGRA_MMCRAB_BASE 0x0E000000 1533cf3183fSVarun Wadekar 1543cf3183fSVarun Wadekar /******************************************************************************* 1553cf3183fSVarun Wadekar * Tegra SMMU Controller constants 1563cf3183fSVarun Wadekar ******************************************************************************/ 1573cf3183fSVarun Wadekar #define TEGRA_SMMU_BASE 0x12000000 1583cf3183fSVarun Wadekar 159d48c0c45SVarun Wadekar /******************************************************************************* 160d48c0c45SVarun Wadekar * Tegra TZRAM constants 161d48c0c45SVarun Wadekar ******************************************************************************/ 162d48c0c45SVarun Wadekar #define TEGRA_TZRAM_BASE 0x30000000 163d48c0c45SVarun Wadekar #define TEGRA_TZRAM_SIZE 0x50000 164d48c0c45SVarun Wadekar 1653cf3183fSVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 166