13cf3183fSVarun Wadekar /* 250cd8646SVarun Wadekar * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53cf3183fSVarun Wadekar */ 63cf3183fSVarun Wadekar 73cf3183fSVarun Wadekar #ifndef __TEGRA_DEF_H__ 83cf3183fSVarun Wadekar #define __TEGRA_DEF_H__ 93cf3183fSVarun Wadekar 103cf3183fSVarun Wadekar /******************************************************************************* 11dec349c8SVarun Wadekar * MCE apertures used by the ARI interface 12dec349c8SVarun Wadekar * 13dec349c8SVarun Wadekar * Aperture 0 - Cpu0 (ARM Cortex A-57) 14dec349c8SVarun Wadekar * Aperture 1 - Cpu1 (ARM Cortex A-57) 15dec349c8SVarun Wadekar * Aperture 2 - Cpu2 (ARM Cortex A-57) 16dec349c8SVarun Wadekar * Aperture 3 - Cpu3 (ARM Cortex A-57) 17dec349c8SVarun Wadekar * Aperture 4 - Cpu4 (Denver15) 18dec349c8SVarun Wadekar * Aperture 5 - Cpu5 (Denver15) 19dec349c8SVarun Wadekar ******************************************************************************/ 20dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_0_OFFSET 0x0 21dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_1_OFFSET 0x10000 22dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_2_OFFSET 0x20000 23dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_3_OFFSET 0x30000 24dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_4_OFFSET 0x40000 25dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_5_OFFSET 0x50000 26dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET 27dec349c8SVarun Wadekar 28dec349c8SVarun Wadekar /* number of apertures */ 29dec349c8SVarun Wadekar #define MCE_ARI_APERTURES_MAX 6 30dec349c8SVarun Wadekar 31dec349c8SVarun Wadekar /* each ARI aperture is 64KB */ 32dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_SIZE 0x10000 33dec349c8SVarun Wadekar 34dec349c8SVarun Wadekar /******************************************************************************* 35dec349c8SVarun Wadekar * CPU core id macros for the MCE_ONLINE_CORE ARI 36dec349c8SVarun Wadekar ******************************************************************************/ 37dec349c8SVarun Wadekar #define MCE_CORE_ID_MAX 8 38dec349c8SVarun Wadekar #define MCE_CORE_ID_MASK 0x7 39dec349c8SVarun Wadekar 40dec349c8SVarun Wadekar /******************************************************************************* 417afd4637SVarun Wadekar * These values are used by the PSCI implementation during the `CPU_SUSPEND` 427afd4637SVarun Wadekar * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 437afd4637SVarun Wadekar * parameter. 443cf3183fSVarun Wadekar ******************************************************************************/ 457afd4637SVarun Wadekar #define PSTATE_ID_CORE_IDLE 6 467afd4637SVarun Wadekar #define PSTATE_ID_CORE_POWERDN 7 477afd4637SVarun Wadekar #define PSTATE_ID_SOC_POWERDN 2 487afd4637SVarun Wadekar 497afd4637SVarun Wadekar /******************************************************************************* 507afd4637SVarun Wadekar * Platform power states (used by PSCI framework) 517afd4637SVarun Wadekar * 527afd4637SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 537afd4637SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 547afd4637SVarun Wadekar ******************************************************************************/ 557afd4637SVarun Wadekar #define PLAT_MAX_RET_STATE 1 567afd4637SVarun Wadekar #define PLAT_MAX_OFF_STATE 8 573cf3183fSVarun Wadekar 583cf3183fSVarun Wadekar /******************************************************************************* 593cf3183fSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 603cf3183fSVarun Wadekar ******************************************************************************/ 613cf3183fSVarun Wadekar #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 623cf3183fSVarun Wadekar #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 633cf3183fSVarun Wadekar #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 643cf3183fSVarun Wadekar #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 653cf3183fSVarun Wadekar #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 663cf3183fSVarun Wadekar #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 673cf3183fSVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 683cf3183fSVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 693cf3183fSVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 703cf3183fSVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 713cf3183fSVarun Wadekar 723cf3183fSVarun Wadekar /******************************************************************************* 7350cd8646SVarun Wadekar * Secure IRQ definitions 7450cd8646SVarun Wadekar ******************************************************************************/ 7550cd8646SVarun Wadekar #define TEGRA186_TOP_WDT_IRQ 49 7650cd8646SVarun Wadekar #define TEGRA186_AON_WDT_IRQ 50 7750cd8646SVarun Wadekar 7850cd8646SVarun Wadekar #define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */ 7950cd8646SVarun Wadekar 8050cd8646SVarun Wadekar /******************************************************************************* 813cf3183fSVarun Wadekar * Tegra Miscellanous register constants 823cf3183fSVarun Wadekar ******************************************************************************/ 833cf3183fSVarun Wadekar #define TEGRA_MISC_BASE 0x00100000 84be87d920SVarun Wadekar #define HARDWARE_REVISION_OFFSET 0x4 85abd3a91dSVarun Wadekar 8650402b17SVarun Wadekar #define MISCREG_PFCFG 0x200C 873cf3183fSVarun Wadekar 883cf3183fSVarun Wadekar /******************************************************************************* 89e64ce3abSVarun Wadekar * Tegra TSA Controller constants 90e64ce3abSVarun Wadekar ******************************************************************************/ 91e64ce3abSVarun Wadekar #define TEGRA_TSA_BASE 0x02400000 92e64ce3abSVarun Wadekar 93e64ce3abSVarun Wadekar /******************************************************************************* 942dd7d41aSVarun Wadekar * TSA configuration registers 952dd7d41aSVarun Wadekar ******************************************************************************/ 962dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010 972dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 982dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038 992dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 1002dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010 1012dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 1022dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008 1032dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 1042dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008 1052dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100 1062dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018 1072dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 1082dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018 1092dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 1102dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028 1112dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 1122dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018 1132dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 1142dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008 1152dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 1162dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018 1172dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 1182dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028 1192dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 1202dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038 1212dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 1222dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008 1232dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 1242dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018 1252dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 1262dd7d41aSVarun Wadekar 1272dd7d41aSVarun Wadekar #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) 1282dd7d41aSVarun Wadekar #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) 1292dd7d41aSVarun Wadekar 1302dd7d41aSVarun Wadekar /******************************************************************************* 1313cf3183fSVarun Wadekar * Tegra Memory Controller constants 1323cf3183fSVarun Wadekar ******************************************************************************/ 1333cf3183fSVarun Wadekar #define TEGRA_MC_STREAMID_BASE 0x02C00000 1343cf3183fSVarun Wadekar #define TEGRA_MC_BASE 0x02C10000 1353cf3183fSVarun Wadekar 1369d42d23aSVarun Wadekar /* General Security Carveout register macros */ 1379d42d23aSVarun Wadekar #define MC_GSC_CONFIG_REGS_SIZE 0x40UL 1389d42d23aSVarun Wadekar #define MC_GSC_LOCK_CFG_SETTINGS_BIT (1UL << 1) 1399d42d23aSVarun Wadekar #define MC_GSC_ENABLE_TZ_LOCK_BIT (1UL << 0) 1409d42d23aSVarun Wadekar #define MC_GSC_SIZE_RANGE_4KB_SHIFT 27UL 1419d42d23aSVarun Wadekar #define MC_GSC_BASE_LO_SHIFT 12UL 1429d42d23aSVarun Wadekar #define MC_GSC_BASE_LO_MASK 0xFFFFFUL 1439d42d23aSVarun Wadekar #define MC_GSC_BASE_HI_SHIFT 0UL 1449d42d23aSVarun Wadekar #define MC_GSC_BASE_HI_MASK 3UL 1459d42d23aSVarun Wadekar 1460258840eSVarun Wadekar /* TZDRAM carveout configuration registers */ 1470258840eSVarun Wadekar #define MC_SECURITY_CFG0_0 0x70 1480258840eSVarun Wadekar #define MC_SECURITY_CFG1_0 0x74 1490258840eSVarun Wadekar #define MC_SECURITY_CFG3_0 0x9BC 1500258840eSVarun Wadekar 1510258840eSVarun Wadekar /* Video Memory carveout configuration registers */ 1520258840eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI 0x978 1530258840eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO 0x648 1549d42d23aSVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB 0x64C 1559d42d23aSVarun Wadekar 1569d42d23aSVarun Wadekar /* 1579d42d23aSVarun Wadekar * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the 1589d42d23aSVarun Wadekar * non-overlapping Video memory region 1599d42d23aSVarun Wadekar */ 1609d42d23aSVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0 1619d42d23aSVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4 1629d42d23aSVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8 1639d42d23aSVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC 1649d42d23aSVarun Wadekar #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0 1650258840eSVarun Wadekar 1660258840eSVarun Wadekar /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 1670258840eSVarun Wadekar #define MC_TZRAM_CARVEOUT_CFG 0x2190 1689d42d23aSVarun Wadekar #define MC_TZRAM_BASE_LO 0x2194 1699d42d23aSVarun Wadekar #define MC_TZRAM_BASE_HI 0x2198 1709d42d23aSVarun Wadekar #define MC_TZRAM_SIZE 0x219C 1719d42d23aSVarun Wadekar #define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0 1720258840eSVarun Wadekar 1733cf3183fSVarun Wadekar /******************************************************************************* 1743cf3183fSVarun Wadekar * Tegra UART Controller constants 1753cf3183fSVarun Wadekar ******************************************************************************/ 1763cf3183fSVarun Wadekar #define TEGRA_UARTA_BASE 0x03100000 1773cf3183fSVarun Wadekar #define TEGRA_UARTB_BASE 0x03110000 1783cf3183fSVarun Wadekar #define TEGRA_UARTC_BASE 0x0C280000 1793cf3183fSVarun Wadekar #define TEGRA_UARTD_BASE 0x03130000 1803cf3183fSVarun Wadekar #define TEGRA_UARTE_BASE 0x03140000 1813cf3183fSVarun Wadekar #define TEGRA_UARTF_BASE 0x03150000 1823cf3183fSVarun Wadekar #define TEGRA_UARTG_BASE 0x0C290000 1833cf3183fSVarun Wadekar 1843cf3183fSVarun Wadekar /******************************************************************************* 1851eed3838SVarun Wadekar * Tegra Fuse Controller related constants 1861eed3838SVarun Wadekar ******************************************************************************/ 1871eed3838SVarun Wadekar #define TEGRA_FUSE_BASE 0x03820000 1881eed3838SVarun Wadekar #define OPT_SUBREVISION 0x248 1891eed3838SVarun Wadekar #define SUBREVISION_MASK 0xFF 1901eed3838SVarun Wadekar 1911eed3838SVarun Wadekar /******************************************************************************* 1923cf3183fSVarun Wadekar * GICv2 & interrupt handling related constants 1933cf3183fSVarun Wadekar ******************************************************************************/ 1943cf3183fSVarun Wadekar #define TEGRA_GICD_BASE 0x03881000 1953cf3183fSVarun Wadekar #define TEGRA_GICC_BASE 0x03882000 1963cf3183fSVarun Wadekar 1973cf3183fSVarun Wadekar /******************************************************************************* 19850402b17SVarun Wadekar * Security Engine related constants 19950402b17SVarun Wadekar ******************************************************************************/ 20050402b17SVarun Wadekar #define TEGRA_SE0_BASE 0x03AC0000 20150402b17SVarun Wadekar #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C 20250402b17SVarun Wadekar #define TEGRA_PKA1_BASE 0x03AD0000 20350402b17SVarun Wadekar #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 20450402b17SVarun Wadekar #define TEGRA_RNG1_BASE 0x03AE0000 20550402b17SVarun Wadekar #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 20650402b17SVarun Wadekar 20750402b17SVarun Wadekar /******************************************************************************* 2083cf3183fSVarun Wadekar * Tegra Clock and Reset Controller constants 2093cf3183fSVarun Wadekar ******************************************************************************/ 2103cf3183fSVarun Wadekar #define TEGRA_CAR_RESET_BASE 0x05000000 2113cf3183fSVarun Wadekar 2123cf3183fSVarun Wadekar /******************************************************************************* 2133cf3183fSVarun Wadekar * Tegra micro-seconds timer constants 2143cf3183fSVarun Wadekar ******************************************************************************/ 2153cf3183fSVarun Wadekar #define TEGRA_TMRUS_BASE 0x0C2E0000 216e99eeec6SSteven Kao #define TEGRA_TMRUS_SIZE 0x1000 2173cf3183fSVarun Wadekar 2183cf3183fSVarun Wadekar /******************************************************************************* 2193cf3183fSVarun Wadekar * Tegra Power Mgmt Controller constants 2203cf3183fSVarun Wadekar ******************************************************************************/ 2213cf3183fSVarun Wadekar #define TEGRA_PMC_BASE 0x0C360000 2223cf3183fSVarun Wadekar 2233cf3183fSVarun Wadekar /******************************************************************************* 2243cf3183fSVarun Wadekar * Tegra scratch registers constants 2253cf3183fSVarun Wadekar ******************************************************************************/ 2263cf3183fSVarun Wadekar #define TEGRA_SCRATCH_BASE 0x0C390000 227cb38550cSVarun Wadekar #define SECURE_SCRATCH_RSV1_LO 0x658 228cb38550cSVarun Wadekar #define SECURE_SCRATCH_RSV1_HI 0x65C 22950402b17SVarun Wadekar #define SECURE_SCRATCH_RSV6 0x680 23050402b17SVarun Wadekar #define SECURE_SCRATCH_RSV11_LO 0x6A8 23150402b17SVarun Wadekar #define SECURE_SCRATCH_RSV11_HI 0x6AC 23248afb167SVarun Wadekar #define SECURE_SCRATCH_RSV53_LO 0x7F8 23348afb167SVarun Wadekar #define SECURE_SCRATCH_RSV53_HI 0x7FC 234719f3ec2SHarvey Hsieh #define SECURE_SCRATCH_RSV54_HI 0x804 235719f3ec2SHarvey Hsieh #define SECURE_SCRATCH_RSV55_LO 0x808 236719f3ec2SHarvey Hsieh #define SECURE_SCRATCH_RSV55_HI 0x80C 2373cf3183fSVarun Wadekar 2383cf3183fSVarun Wadekar /******************************************************************************* 239691bc22dSVarun Wadekar * Tegra Memory Mapped Control Register Access constants 2403cf3183fSVarun Wadekar ******************************************************************************/ 2413cf3183fSVarun Wadekar #define TEGRA_MMCRAB_BASE 0x0E000000 2423cf3183fSVarun Wadekar 2433cf3183fSVarun Wadekar /******************************************************************************* 244691bc22dSVarun Wadekar * Tegra Memory Mapped Activity Monitor Register Access constants 245691bc22dSVarun Wadekar ******************************************************************************/ 246691bc22dSVarun Wadekar #define TEGRA_ARM_ACTMON_CTR_BASE 0x0E060000 247691bc22dSVarun Wadekar #define TEGRA_DENVER_ACTMON_CTR_BASE 0x0E070000 248691bc22dSVarun Wadekar 249691bc22dSVarun Wadekar /******************************************************************************* 2503cf3183fSVarun Wadekar * Tegra SMMU Controller constants 2513cf3183fSVarun Wadekar ******************************************************************************/ 252c459206dSPritesh Raithatha #define TEGRA_SMMU0_BASE 0x12000000 2533cf3183fSVarun Wadekar 254d48c0c45SVarun Wadekar /******************************************************************************* 255d48c0c45SVarun Wadekar * Tegra TZRAM constants 256d48c0c45SVarun Wadekar ******************************************************************************/ 257d48c0c45SVarun Wadekar #define TEGRA_TZRAM_BASE 0x30000000 2582f583f8eSVarun Wadekar #define TEGRA_TZRAM_SIZE 0x40000 259d48c0c45SVarun Wadekar 2603cf3183fSVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 261