13cf3183fSVarun Wadekar /* 250cd8646SVarun Wadekar * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 43cf3183fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 53cf3183fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 63cf3183fSVarun Wadekar * 73cf3183fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 83cf3183fSVarun Wadekar * list of conditions and the following disclaimer. 93cf3183fSVarun Wadekar * 103cf3183fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 113cf3183fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 123cf3183fSVarun Wadekar * and/or other materials provided with the distribution. 133cf3183fSVarun Wadekar * 143cf3183fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 153cf3183fSVarun Wadekar * to endorse or promote products derived from this software without specific 163cf3183fSVarun Wadekar * prior written permission. 173cf3183fSVarun Wadekar * 183cf3183fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 193cf3183fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 203cf3183fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 213cf3183fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 223cf3183fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 233cf3183fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 243cf3183fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 253cf3183fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 263cf3183fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 273cf3183fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 283cf3183fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 293cf3183fSVarun Wadekar */ 303cf3183fSVarun Wadekar 313cf3183fSVarun Wadekar #ifndef __TEGRA_DEF_H__ 323cf3183fSVarun Wadekar #define __TEGRA_DEF_H__ 333cf3183fSVarun Wadekar 343cf3183fSVarun Wadekar /******************************************************************************* 35dec349c8SVarun Wadekar * MCE apertures used by the ARI interface 36dec349c8SVarun Wadekar * 37dec349c8SVarun Wadekar * Aperture 0 - Cpu0 (ARM Cortex A-57) 38dec349c8SVarun Wadekar * Aperture 1 - Cpu1 (ARM Cortex A-57) 39dec349c8SVarun Wadekar * Aperture 2 - Cpu2 (ARM Cortex A-57) 40dec349c8SVarun Wadekar * Aperture 3 - Cpu3 (ARM Cortex A-57) 41dec349c8SVarun Wadekar * Aperture 4 - Cpu4 (Denver15) 42dec349c8SVarun Wadekar * Aperture 5 - Cpu5 (Denver15) 43dec349c8SVarun Wadekar ******************************************************************************/ 44dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_0_OFFSET 0x0 45dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_1_OFFSET 0x10000 46dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_2_OFFSET 0x20000 47dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_3_OFFSET 0x30000 48dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_4_OFFSET 0x40000 49dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_5_OFFSET 0x50000 50dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET 51dec349c8SVarun Wadekar 52dec349c8SVarun Wadekar /* number of apertures */ 53dec349c8SVarun Wadekar #define MCE_ARI_APERTURES_MAX 6 54dec349c8SVarun Wadekar 55dec349c8SVarun Wadekar /* each ARI aperture is 64KB */ 56dec349c8SVarun Wadekar #define MCE_ARI_APERTURE_SIZE 0x10000 57dec349c8SVarun Wadekar 58dec349c8SVarun Wadekar /******************************************************************************* 59dec349c8SVarun Wadekar * CPU core id macros for the MCE_ONLINE_CORE ARI 60dec349c8SVarun Wadekar ******************************************************************************/ 61dec349c8SVarun Wadekar #define MCE_CORE_ID_MAX 8 62dec349c8SVarun Wadekar #define MCE_CORE_ID_MASK 0x7 63dec349c8SVarun Wadekar 64dec349c8SVarun Wadekar /******************************************************************************* 657afd4637SVarun Wadekar * These values are used by the PSCI implementation during the `CPU_SUSPEND` 667afd4637SVarun Wadekar * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 677afd4637SVarun Wadekar * parameter. 683cf3183fSVarun Wadekar ******************************************************************************/ 697afd4637SVarun Wadekar #define PSTATE_ID_CORE_IDLE 6 707afd4637SVarun Wadekar #define PSTATE_ID_CORE_POWERDN 7 717afd4637SVarun Wadekar #define PSTATE_ID_SOC_POWERDN 2 727afd4637SVarun Wadekar 737afd4637SVarun Wadekar /******************************************************************************* 747afd4637SVarun Wadekar * Platform power states (used by PSCI framework) 757afd4637SVarun Wadekar * 767afd4637SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 777afd4637SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 787afd4637SVarun Wadekar ******************************************************************************/ 797afd4637SVarun Wadekar #define PLAT_MAX_RET_STATE 1 807afd4637SVarun Wadekar #define PLAT_MAX_OFF_STATE 8 813cf3183fSVarun Wadekar 823cf3183fSVarun Wadekar /******************************************************************************* 833cf3183fSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 843cf3183fSVarun Wadekar ******************************************************************************/ 853cf3183fSVarun Wadekar #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 863cf3183fSVarun Wadekar #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 873cf3183fSVarun Wadekar #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 883cf3183fSVarun Wadekar #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 893cf3183fSVarun Wadekar #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 903cf3183fSVarun Wadekar #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 913cf3183fSVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 923cf3183fSVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 933cf3183fSVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 943cf3183fSVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 953cf3183fSVarun Wadekar 963cf3183fSVarun Wadekar /******************************************************************************* 9750cd8646SVarun Wadekar * Secure IRQ definitions 9850cd8646SVarun Wadekar ******************************************************************************/ 9950cd8646SVarun Wadekar #define TEGRA186_TOP_WDT_IRQ 49 10050cd8646SVarun Wadekar #define TEGRA186_AON_WDT_IRQ 50 10150cd8646SVarun Wadekar 10250cd8646SVarun Wadekar #define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */ 10350cd8646SVarun Wadekar 10450cd8646SVarun Wadekar /******************************************************************************* 1053cf3183fSVarun Wadekar * Tegra Miscellanous register constants 1063cf3183fSVarun Wadekar ******************************************************************************/ 1073cf3183fSVarun Wadekar #define TEGRA_MISC_BASE 0x00100000 108be87d920SVarun Wadekar #define HARDWARE_REVISION_OFFSET 0x4 109abd3a91dSVarun Wadekar 11050402b17SVarun Wadekar #define MISCREG_PFCFG 0x200C 1113cf3183fSVarun Wadekar 1123cf3183fSVarun Wadekar /******************************************************************************* 113e64ce3abSVarun Wadekar * Tegra TSA Controller constants 114e64ce3abSVarun Wadekar ******************************************************************************/ 115e64ce3abSVarun Wadekar #define TEGRA_TSA_BASE 0x02400000 116e64ce3abSVarun Wadekar 117e64ce3abSVarun Wadekar /******************************************************************************* 1182dd7d41aSVarun Wadekar * TSA configuration registers 1192dd7d41aSVarun Wadekar ******************************************************************************/ 1202dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010 1212dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 1222dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038 1232dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 1242dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010 1252dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 1262dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008 1272dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 1282dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008 1292dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100 1302dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018 1312dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 1322dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018 1332dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 1342dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028 1352dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 1362dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018 1372dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 1382dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008 1392dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 1402dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018 1412dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 1422dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028 1432dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 1442dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038 1452dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 1462dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008 1472dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 1482dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018 1492dd7d41aSVarun Wadekar #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 1502dd7d41aSVarun Wadekar 1512dd7d41aSVarun Wadekar #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) 1522dd7d41aSVarun Wadekar #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) 1532dd7d41aSVarun Wadekar 1542dd7d41aSVarun Wadekar /******************************************************************************* 1553cf3183fSVarun Wadekar * Tegra Memory Controller constants 1563cf3183fSVarun Wadekar ******************************************************************************/ 1573cf3183fSVarun Wadekar #define TEGRA_MC_STREAMID_BASE 0x02C00000 1583cf3183fSVarun Wadekar #define TEGRA_MC_BASE 0x02C10000 1593cf3183fSVarun Wadekar 1600258840eSVarun Wadekar /* TZDRAM carveout configuration registers */ 1610258840eSVarun Wadekar #define MC_SECURITY_CFG0_0 0x70 1620258840eSVarun Wadekar #define MC_SECURITY_CFG1_0 0x74 1630258840eSVarun Wadekar #define MC_SECURITY_CFG3_0 0x9BC 1640258840eSVarun Wadekar 1650258840eSVarun Wadekar /* Video Memory carveout configuration registers */ 1660258840eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI 0x978 1670258840eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO 0x648 1680258840eSVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 1690258840eSVarun Wadekar 1700258840eSVarun Wadekar /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 1710258840eSVarun Wadekar #define MC_TZRAM_BASE_LO 0x2194 1720258840eSVarun Wadekar #define TZRAM_BASE_LO_SHIFT 12 1730258840eSVarun Wadekar #define TZRAM_BASE_LO_MASK 0xFFFFF 1740258840eSVarun Wadekar #define MC_TZRAM_BASE_HI 0x2198 1750258840eSVarun Wadekar #define TZRAM_BASE_HI_SHIFT 0 1760258840eSVarun Wadekar #define TZRAM_BASE_HI_MASK 3 1770258840eSVarun Wadekar #define MC_TZRAM_SIZE 0x219C 1780258840eSVarun Wadekar #define TZRAM_SIZE_RANGE_4KB_SHIFT 27 1790258840eSVarun Wadekar 1800258840eSVarun Wadekar #define MC_TZRAM_CARVEOUT_CFG 0x2190 1810258840eSVarun Wadekar #define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1) 1820258840eSVarun Wadekar #define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0) 1830258840eSVarun Wadekar #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0 1840258840eSVarun Wadekar #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4 1850258840eSVarun Wadekar #define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25) 1860258840eSVarun Wadekar #define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7) 1870258840eSVarun Wadekar #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8 1880258840eSVarun Wadekar #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC 1890258840eSVarun Wadekar #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0 1900258840eSVarun Wadekar #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4 1910258840eSVarun Wadekar 1920258840eSVarun Wadekar #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8 1930258840eSVarun Wadekar #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC 1940258840eSVarun Wadekar #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0 1950258840eSVarun Wadekar #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4 1960258840eSVarun Wadekar #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8 1970258840eSVarun Wadekar #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC 1980258840eSVarun Wadekar 1993cf3183fSVarun Wadekar /******************************************************************************* 2003cf3183fSVarun Wadekar * Tegra UART Controller constants 2013cf3183fSVarun Wadekar ******************************************************************************/ 2023cf3183fSVarun Wadekar #define TEGRA_UARTA_BASE 0x03100000 2033cf3183fSVarun Wadekar #define TEGRA_UARTB_BASE 0x03110000 2043cf3183fSVarun Wadekar #define TEGRA_UARTC_BASE 0x0C280000 2053cf3183fSVarun Wadekar #define TEGRA_UARTD_BASE 0x03130000 2063cf3183fSVarun Wadekar #define TEGRA_UARTE_BASE 0x03140000 2073cf3183fSVarun Wadekar #define TEGRA_UARTF_BASE 0x03150000 2083cf3183fSVarun Wadekar #define TEGRA_UARTG_BASE 0x0C290000 2093cf3183fSVarun Wadekar 2103cf3183fSVarun Wadekar /******************************************************************************* 2111eed3838SVarun Wadekar * Tegra Fuse Controller related constants 2121eed3838SVarun Wadekar ******************************************************************************/ 2131eed3838SVarun Wadekar #define TEGRA_FUSE_BASE 0x03820000 2141eed3838SVarun Wadekar #define OPT_SUBREVISION 0x248 2151eed3838SVarun Wadekar #define SUBREVISION_MASK 0xFF 2161eed3838SVarun Wadekar 2171eed3838SVarun Wadekar /******************************************************************************* 2183cf3183fSVarun Wadekar * GICv2 & interrupt handling related constants 2193cf3183fSVarun Wadekar ******************************************************************************/ 2203cf3183fSVarun Wadekar #define TEGRA_GICD_BASE 0x03881000 2213cf3183fSVarun Wadekar #define TEGRA_GICC_BASE 0x03882000 2223cf3183fSVarun Wadekar 2233cf3183fSVarun Wadekar /******************************************************************************* 22450402b17SVarun Wadekar * Security Engine related constants 22550402b17SVarun Wadekar ******************************************************************************/ 22650402b17SVarun Wadekar #define TEGRA_SE0_BASE 0x03AC0000 22750402b17SVarun Wadekar #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C 22850402b17SVarun Wadekar #define TEGRA_PKA1_BASE 0x03AD0000 22950402b17SVarun Wadekar #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 23050402b17SVarun Wadekar #define TEGRA_RNG1_BASE 0x03AE0000 23150402b17SVarun Wadekar #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 23250402b17SVarun Wadekar 23350402b17SVarun Wadekar /******************************************************************************* 2343cf3183fSVarun Wadekar * Tegra Clock and Reset Controller constants 2353cf3183fSVarun Wadekar ******************************************************************************/ 2363cf3183fSVarun Wadekar #define TEGRA_CAR_RESET_BASE 0x05000000 2373cf3183fSVarun Wadekar 2383cf3183fSVarun Wadekar /******************************************************************************* 2393cf3183fSVarun Wadekar * Tegra micro-seconds timer constants 2403cf3183fSVarun Wadekar ******************************************************************************/ 2413cf3183fSVarun Wadekar #define TEGRA_TMRUS_BASE 0x0C2E0000 2423cf3183fSVarun Wadekar 2433cf3183fSVarun Wadekar /******************************************************************************* 2443cf3183fSVarun Wadekar * Tegra Power Mgmt Controller constants 2453cf3183fSVarun Wadekar ******************************************************************************/ 2463cf3183fSVarun Wadekar #define TEGRA_PMC_BASE 0x0C360000 2473cf3183fSVarun Wadekar 2483cf3183fSVarun Wadekar /******************************************************************************* 2493cf3183fSVarun Wadekar * Tegra scratch registers constants 2503cf3183fSVarun Wadekar ******************************************************************************/ 2513cf3183fSVarun Wadekar #define TEGRA_SCRATCH_BASE 0x0C390000 252cb38550cSVarun Wadekar #define SECURE_SCRATCH_RSV1_LO 0x658 253cb38550cSVarun Wadekar #define SECURE_SCRATCH_RSV1_HI 0x65C 25450402b17SVarun Wadekar #define SECURE_SCRATCH_RSV6 0x680 25550402b17SVarun Wadekar #define SECURE_SCRATCH_RSV11_LO 0x6A8 25650402b17SVarun Wadekar #define SECURE_SCRATCH_RSV11_HI 0x6AC 25748afb167SVarun Wadekar #define SECURE_SCRATCH_RSV53_LO 0x7F8 25848afb167SVarun Wadekar #define SECURE_SCRATCH_RSV53_HI 0x7FC 259719f3ec2SHarvey Hsieh #define SECURE_SCRATCH_RSV54_HI 0x804 260719f3ec2SHarvey Hsieh #define SECURE_SCRATCH_RSV55_LO 0x808 261719f3ec2SHarvey Hsieh #define SECURE_SCRATCH_RSV55_HI 0x80C 2623cf3183fSVarun Wadekar 2633cf3183fSVarun Wadekar /******************************************************************************* 264*691bc22dSVarun Wadekar * Tegra Memory Mapped Control Register Access constants 2653cf3183fSVarun Wadekar ******************************************************************************/ 2663cf3183fSVarun Wadekar #define TEGRA_MMCRAB_BASE 0x0E000000 2673cf3183fSVarun Wadekar 2683cf3183fSVarun Wadekar /******************************************************************************* 269*691bc22dSVarun Wadekar * Tegra Memory Mapped Activity Monitor Register Access constants 270*691bc22dSVarun Wadekar ******************************************************************************/ 271*691bc22dSVarun Wadekar #define TEGRA_ARM_ACTMON_CTR_BASE 0x0E060000 272*691bc22dSVarun Wadekar #define TEGRA_DENVER_ACTMON_CTR_BASE 0x0E070000 273*691bc22dSVarun Wadekar 274*691bc22dSVarun Wadekar /******************************************************************************* 2753cf3183fSVarun Wadekar * Tegra SMMU Controller constants 2763cf3183fSVarun Wadekar ******************************************************************************/ 2773cf3183fSVarun Wadekar #define TEGRA_SMMU_BASE 0x12000000 2783cf3183fSVarun Wadekar 279d48c0c45SVarun Wadekar /******************************************************************************* 280d48c0c45SVarun Wadekar * Tegra TZRAM constants 281d48c0c45SVarun Wadekar ******************************************************************************/ 282d48c0c45SVarun Wadekar #define TEGRA_TZRAM_BASE 0x30000000 2832f583f8eSVarun Wadekar #define TEGRA_TZRAM_SIZE 0x40000 284d48c0c45SVarun Wadekar 2853cf3183fSVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 286