13cf3183fSVarun Wadekar /* 2*50cd8646SVarun Wadekar * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 43cf3183fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 53cf3183fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 63cf3183fSVarun Wadekar * 73cf3183fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 83cf3183fSVarun Wadekar * list of conditions and the following disclaimer. 93cf3183fSVarun Wadekar * 103cf3183fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 113cf3183fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 123cf3183fSVarun Wadekar * and/or other materials provided with the distribution. 133cf3183fSVarun Wadekar * 143cf3183fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 153cf3183fSVarun Wadekar * to endorse or promote products derived from this software without specific 163cf3183fSVarun Wadekar * prior written permission. 173cf3183fSVarun Wadekar * 183cf3183fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 193cf3183fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 203cf3183fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 213cf3183fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 223cf3183fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 233cf3183fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 243cf3183fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 253cf3183fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 263cf3183fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 273cf3183fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 283cf3183fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 293cf3183fSVarun Wadekar */ 303cf3183fSVarun Wadekar 313cf3183fSVarun Wadekar #ifndef __TEGRA_DEF_H__ 323cf3183fSVarun Wadekar #define __TEGRA_DEF_H__ 333cf3183fSVarun Wadekar 343cf3183fSVarun Wadekar #include <platform_def.h> 353cf3183fSVarun Wadekar 363cf3183fSVarun Wadekar /******************************************************************************* 377afd4637SVarun Wadekar * These values are used by the PSCI implementation during the `CPU_SUSPEND` 387afd4637SVarun Wadekar * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 397afd4637SVarun Wadekar * parameter. 403cf3183fSVarun Wadekar ******************************************************************************/ 417afd4637SVarun Wadekar #define PSTATE_ID_CORE_IDLE 6 427afd4637SVarun Wadekar #define PSTATE_ID_CORE_POWERDN 7 437afd4637SVarun Wadekar #define PSTATE_ID_SOC_POWERDN 2 447afd4637SVarun Wadekar 457afd4637SVarun Wadekar /******************************************************************************* 467afd4637SVarun Wadekar * Platform power states (used by PSCI framework) 477afd4637SVarun Wadekar * 487afd4637SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 497afd4637SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 507afd4637SVarun Wadekar ******************************************************************************/ 517afd4637SVarun Wadekar #define PLAT_MAX_RET_STATE 1 527afd4637SVarun Wadekar #define PLAT_MAX_OFF_STATE 8 533cf3183fSVarun Wadekar 543cf3183fSVarun Wadekar /******************************************************************************* 553cf3183fSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 563cf3183fSVarun Wadekar ******************************************************************************/ 573cf3183fSVarun Wadekar #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 583cf3183fSVarun Wadekar #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 593cf3183fSVarun Wadekar #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 603cf3183fSVarun Wadekar #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 613cf3183fSVarun Wadekar #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 623cf3183fSVarun Wadekar #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 633cf3183fSVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 643cf3183fSVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 653cf3183fSVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 663cf3183fSVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 673cf3183fSVarun Wadekar 683cf3183fSVarun Wadekar /******************************************************************************* 69*50cd8646SVarun Wadekar * Secure IRQ definitions 70*50cd8646SVarun Wadekar ******************************************************************************/ 71*50cd8646SVarun Wadekar #define TEGRA186_TOP_WDT_IRQ 49 72*50cd8646SVarun Wadekar #define TEGRA186_AON_WDT_IRQ 50 73*50cd8646SVarun Wadekar 74*50cd8646SVarun Wadekar #define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */ 75*50cd8646SVarun Wadekar 76*50cd8646SVarun Wadekar /******************************************************************************* 773cf3183fSVarun Wadekar * Tegra Miscellanous register constants 783cf3183fSVarun Wadekar ******************************************************************************/ 793cf3183fSVarun Wadekar #define TEGRA_MISC_BASE 0x00100000 80be87d920SVarun Wadekar #define HARDWARE_REVISION_OFFSET 0x4 81be87d920SVarun Wadekar #define HARDWARE_MINOR_REVISION_MASK 0xf0000 82be87d920SVarun Wadekar #define HARDWARE_MINOR_REVISION_SHIFT 0x10 83be87d920SVarun Wadekar #define HARDWARE_REVISION_A01 1 843cf3183fSVarun Wadekar 853cf3183fSVarun Wadekar /******************************************************************************* 863cf3183fSVarun Wadekar * Tegra Memory Controller constants 873cf3183fSVarun Wadekar ******************************************************************************/ 883cf3183fSVarun Wadekar #define TEGRA_MC_STREAMID_BASE 0x02C00000 893cf3183fSVarun Wadekar #define TEGRA_MC_BASE 0x02C10000 903cf3183fSVarun Wadekar 913cf3183fSVarun Wadekar /******************************************************************************* 923cf3183fSVarun Wadekar * Tegra UART Controller constants 933cf3183fSVarun Wadekar ******************************************************************************/ 943cf3183fSVarun Wadekar #define TEGRA_UARTA_BASE 0x03100000 953cf3183fSVarun Wadekar #define TEGRA_UARTB_BASE 0x03110000 963cf3183fSVarun Wadekar #define TEGRA_UARTC_BASE 0x0C280000 973cf3183fSVarun Wadekar #define TEGRA_UARTD_BASE 0x03130000 983cf3183fSVarun Wadekar #define TEGRA_UARTE_BASE 0x03140000 993cf3183fSVarun Wadekar #define TEGRA_UARTF_BASE 0x03150000 1003cf3183fSVarun Wadekar #define TEGRA_UARTG_BASE 0x0C290000 1013cf3183fSVarun Wadekar 1023cf3183fSVarun Wadekar /******************************************************************************* 1033cf3183fSVarun Wadekar * GICv2 & interrupt handling related constants 1043cf3183fSVarun Wadekar ******************************************************************************/ 1053cf3183fSVarun Wadekar #define TEGRA_GICD_BASE 0x03881000 1063cf3183fSVarun Wadekar #define TEGRA_GICC_BASE 0x03882000 1073cf3183fSVarun Wadekar 1083cf3183fSVarun Wadekar /******************************************************************************* 1093cf3183fSVarun Wadekar * Tegra Clock and Reset Controller constants 1103cf3183fSVarun Wadekar ******************************************************************************/ 1113cf3183fSVarun Wadekar #define TEGRA_CAR_RESET_BASE 0x05000000 1123cf3183fSVarun Wadekar 1133cf3183fSVarun Wadekar /******************************************************************************* 1143cf3183fSVarun Wadekar * Tegra micro-seconds timer constants 1153cf3183fSVarun Wadekar ******************************************************************************/ 1163cf3183fSVarun Wadekar #define TEGRA_TMRUS_BASE 0x0C2E0000 1173cf3183fSVarun Wadekar 1183cf3183fSVarun Wadekar /******************************************************************************* 1193cf3183fSVarun Wadekar * Tegra Power Mgmt Controller constants 1203cf3183fSVarun Wadekar ******************************************************************************/ 1213cf3183fSVarun Wadekar #define TEGRA_PMC_BASE 0x0C360000 1223cf3183fSVarun Wadekar 1233cf3183fSVarun Wadekar /******************************************************************************* 1243cf3183fSVarun Wadekar * Tegra scratch registers constants 1253cf3183fSVarun Wadekar ******************************************************************************/ 1263cf3183fSVarun Wadekar #define TEGRA_SCRATCH_BASE 0x0C390000 1273cf3183fSVarun Wadekar 1283cf3183fSVarun Wadekar /******************************************************************************* 1293cf3183fSVarun Wadekar * Tegra Memory Mapped Control Register Access Bus constants 1303cf3183fSVarun Wadekar ******************************************************************************/ 1313cf3183fSVarun Wadekar #define TEGRA_MMCRAB_BASE 0x0E000000 1323cf3183fSVarun Wadekar 1333cf3183fSVarun Wadekar /******************************************************************************* 1343cf3183fSVarun Wadekar * Tegra SMMU Controller constants 1353cf3183fSVarun Wadekar ******************************************************************************/ 1363cf3183fSVarun Wadekar #define TEGRA_SMMU_BASE 0x12000000 1373cf3183fSVarun Wadekar 138d48c0c45SVarun Wadekar /******************************************************************************* 139d48c0c45SVarun Wadekar * Tegra TZRAM constants 140d48c0c45SVarun Wadekar ******************************************************************************/ 141d48c0c45SVarun Wadekar #define TEGRA_TZRAM_BASE 0x30000000 142d48c0c45SVarun Wadekar #define TEGRA_TZRAM_SIZE 0x50000 143d48c0c45SVarun Wadekar 1443cf3183fSVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 145