1*3cf3183fSVarun Wadekar /* 2*3cf3183fSVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*3cf3183fSVarun Wadekar * 4*3cf3183fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*3cf3183fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*3cf3183fSVarun Wadekar * 7*3cf3183fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*3cf3183fSVarun Wadekar * list of conditions and the following disclaimer. 9*3cf3183fSVarun Wadekar * 10*3cf3183fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*3cf3183fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*3cf3183fSVarun Wadekar * and/or other materials provided with the distribution. 13*3cf3183fSVarun Wadekar * 14*3cf3183fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*3cf3183fSVarun Wadekar * to endorse or promote products derived from this software without specific 16*3cf3183fSVarun Wadekar * prior written permission. 17*3cf3183fSVarun Wadekar * 18*3cf3183fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*3cf3183fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*3cf3183fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*3cf3183fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*3cf3183fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*3cf3183fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*3cf3183fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*3cf3183fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*3cf3183fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*3cf3183fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*3cf3183fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*3cf3183fSVarun Wadekar */ 30*3cf3183fSVarun Wadekar 31*3cf3183fSVarun Wadekar #ifndef __TEGRA_DEF_H__ 32*3cf3183fSVarun Wadekar #define __TEGRA_DEF_H__ 33*3cf3183fSVarun Wadekar 34*3cf3183fSVarun Wadekar #include <platform_def.h> 35*3cf3183fSVarun Wadekar 36*3cf3183fSVarun Wadekar /******************************************************************************* 37*3cf3183fSVarun Wadekar * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 38*3cf3183fSVarun Wadekar * call as the `state-id` field in the 'power state' parameter. 39*3cf3183fSVarun Wadekar ******************************************************************************/ 40*3cf3183fSVarun Wadekar #define PLAT_SYS_SUSPEND_STATE_ID 0 41*3cf3183fSVarun Wadekar 42*3cf3183fSVarun Wadekar /******************************************************************************* 43*3cf3183fSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 44*3cf3183fSVarun Wadekar ******************************************************************************/ 45*3cf3183fSVarun Wadekar #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 46*3cf3183fSVarun Wadekar #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 47*3cf3183fSVarun Wadekar #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 48*3cf3183fSVarun Wadekar #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 49*3cf3183fSVarun Wadekar #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 50*3cf3183fSVarun Wadekar #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 51*3cf3183fSVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 52*3cf3183fSVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 53*3cf3183fSVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 54*3cf3183fSVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 55*3cf3183fSVarun Wadekar 56*3cf3183fSVarun Wadekar /******************************************************************************* 57*3cf3183fSVarun Wadekar * Tegra Miscellanous register constants 58*3cf3183fSVarun Wadekar ******************************************************************************/ 59*3cf3183fSVarun Wadekar #define TEGRA_MISC_BASE 0x00100000 60*3cf3183fSVarun Wadekar 61*3cf3183fSVarun Wadekar /******************************************************************************* 62*3cf3183fSVarun Wadekar * Tegra Memory Controller constants 63*3cf3183fSVarun Wadekar ******************************************************************************/ 64*3cf3183fSVarun Wadekar #define TEGRA_MC_STREAMID_BASE 0x02C00000 65*3cf3183fSVarun Wadekar #define TEGRA_MC_BASE 0x02C10000 66*3cf3183fSVarun Wadekar 67*3cf3183fSVarun Wadekar /******************************************************************************* 68*3cf3183fSVarun Wadekar * Tegra UART Controller constants 69*3cf3183fSVarun Wadekar ******************************************************************************/ 70*3cf3183fSVarun Wadekar #define TEGRA_UARTA_BASE 0x03100000 71*3cf3183fSVarun Wadekar #define TEGRA_UARTB_BASE 0x03110000 72*3cf3183fSVarun Wadekar #define TEGRA_UARTC_BASE 0x0C280000 73*3cf3183fSVarun Wadekar #define TEGRA_UARTD_BASE 0x03130000 74*3cf3183fSVarun Wadekar #define TEGRA_UARTE_BASE 0x03140000 75*3cf3183fSVarun Wadekar #define TEGRA_UARTF_BASE 0x03150000 76*3cf3183fSVarun Wadekar #define TEGRA_UARTG_BASE 0x0C290000 77*3cf3183fSVarun Wadekar 78*3cf3183fSVarun Wadekar /******************************************************************************* 79*3cf3183fSVarun Wadekar * GICv2 & interrupt handling related constants 80*3cf3183fSVarun Wadekar ******************************************************************************/ 81*3cf3183fSVarun Wadekar #define TEGRA_GICD_BASE 0x03881000 82*3cf3183fSVarun Wadekar #define TEGRA_GICC_BASE 0x03882000 83*3cf3183fSVarun Wadekar 84*3cf3183fSVarun Wadekar /******************************************************************************* 85*3cf3183fSVarun Wadekar * Tegra Clock and Reset Controller constants 86*3cf3183fSVarun Wadekar ******************************************************************************/ 87*3cf3183fSVarun Wadekar #define TEGRA_CAR_RESET_BASE 0x05000000 88*3cf3183fSVarun Wadekar 89*3cf3183fSVarun Wadekar /******************************************************************************* 90*3cf3183fSVarun Wadekar * Tegra micro-seconds timer constants 91*3cf3183fSVarun Wadekar ******************************************************************************/ 92*3cf3183fSVarun Wadekar #define TEGRA_TMRUS_BASE 0x0C2E0000 93*3cf3183fSVarun Wadekar 94*3cf3183fSVarun Wadekar /******************************************************************************* 95*3cf3183fSVarun Wadekar * Tegra Power Mgmt Controller constants 96*3cf3183fSVarun Wadekar ******************************************************************************/ 97*3cf3183fSVarun Wadekar #define TEGRA_PMC_BASE 0x0C360000 98*3cf3183fSVarun Wadekar 99*3cf3183fSVarun Wadekar /******************************************************************************* 100*3cf3183fSVarun Wadekar * Tegra scratch registers constants 101*3cf3183fSVarun Wadekar ******************************************************************************/ 102*3cf3183fSVarun Wadekar #define TEGRA_SCRATCH_BASE 0x0C390000 103*3cf3183fSVarun Wadekar 104*3cf3183fSVarun Wadekar /******************************************************************************* 105*3cf3183fSVarun Wadekar * Tegra Memory Mapped Control Register Access Bus constants 106*3cf3183fSVarun Wadekar ******************************************************************************/ 107*3cf3183fSVarun Wadekar #define TEGRA_MMCRAB_BASE 0x0E000000 108*3cf3183fSVarun Wadekar 109*3cf3183fSVarun Wadekar /******************************************************************************* 110*3cf3183fSVarun Wadekar * Tegra SMMU Controller constants 111*3cf3183fSVarun Wadekar ******************************************************************************/ 112*3cf3183fSVarun Wadekar #define TEGRA_SMMU_BASE 0x12000000 113*3cf3183fSVarun Wadekar 114*3cf3183fSVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 115