1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <lib/utils_def.h> 12 #include <plat/common/common_def.h> 13 14 #include <tegra_def.h> 15 16 /******************************************************************************* 17 * Generic platform constants 18 ******************************************************************************/ 19 20 /* Size of cacheable stacks */ 21 #ifdef IMAGE_BL31 22 #define PLATFORM_STACK_SIZE U(0x400) 23 #endif 24 25 #define TEGRA_PRIMARY_CPU U(0x0) 26 27 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 28 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 29 PLATFORM_MAX_CPUS_PER_CLUSTER) 30 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 31 PLATFORM_CLUSTER_COUNT + 1) 32 33 /******************************************************************************* 34 * Platform console related constants 35 ******************************************************************************/ 36 #define TEGRA_CONSOLE_BAUDRATE U(115200) 37 #define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000) 38 #define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000) 39 40 /******************************************************************************* 41 * Platform memory map related constants 42 ******************************************************************************/ 43 /* Size of trusted dram */ 44 #define TZDRAM_SIZE U(0x00400000) 45 #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) 46 47 /******************************************************************************* 48 * BL31 specific defines. 49 ******************************************************************************/ 50 #define BL31_SIZE U(0x40000) 51 #define BL31_BASE TZDRAM_BASE 52 #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) 53 #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) 54 #define BL32_LIMIT TZDRAM_END 55 56 /******************************************************************************* 57 * Some data must be aligned on the biggest cache line size in the platform. 58 * This is known only to the platform as it might have a combination of 59 * integrated and external caches. 60 ******************************************************************************/ 61 #define CACHE_WRITEBACK_SHIFT 6 62 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 63 64 #endif /* PLATFORM_DEF_H */ 65