1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include <common_def.h> 12 #include <tegra_def.h> 13 14 /******************************************************************************* 15 * Generic platform constants 16 ******************************************************************************/ 17 18 /* Size of cacheable stacks */ 19 #ifdef IMAGE_BL31 20 #define PLATFORM_STACK_SIZE 0x400 21 #endif 22 23 #define TEGRA_PRIMARY_CPU 0x0 24 25 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 26 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 27 PLATFORM_MAX_CPUS_PER_CLUSTER) 28 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 29 PLATFORM_CLUSTER_COUNT + 1) 30 31 /******************************************************************************* 32 * Platform console related constants 33 ******************************************************************************/ 34 #define TEGRA_CONSOLE_BAUDRATE 115200 35 #define TEGRA_BOOT_UART_CLK_IN_HZ 408000000 36 37 /******************************************************************************* 38 * Platform memory map related constants 39 ******************************************************************************/ 40 /* Size of trusted dram */ 41 #define TZDRAM_SIZE 0x00400000 42 #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) 43 44 /******************************************************************************* 45 * BL31 specific defines. 46 ******************************************************************************/ 47 #define BL31_SIZE 0x40000 48 #define BL31_BASE TZDRAM_BASE 49 #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) 50 #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) 51 #define BL32_LIMIT TZDRAM_END 52 53 /******************************************************************************* 54 * Platform specific page table and MMU setup constants 55 ******************************************************************************/ 56 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 35) 57 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 35) 58 59 /******************************************************************************* 60 * Some data must be aligned on the biggest cache line size in the platform. 61 * This is known only to the platform as it might have a combination of 62 * integrated and external caches. 63 ******************************************************************************/ 64 #define CACHE_WRITEBACK_SHIFT 6 65 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 66 67 #endif /* __PLATFORM_DEF_H__ */ 68