108438e24SVarun Wadekar /* 21d11f73eSSteven Kao * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 342080d48SVarun Wadekar * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 408438e24SVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 608438e24SVarun Wadekar */ 708438e24SVarun Wadekar 8c3cf06f1SAntonio Nino Diaz #ifndef PLATFORM_DEF_H 9c3cf06f1SAntonio Nino Diaz #define PLATFORM_DEF_H 1008438e24SVarun Wadekar 1108438e24SVarun Wadekar #include <arch.h> 1209d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 1309d40e0eSAntonio Nino Diaz 1471cb26eaSVarun Wadekar #include <tegra_def.h> 1508438e24SVarun Wadekar 162bf1085dSKalyani Chidambaram /******************************************************************************* 172bf1085dSKalyani Chidambaram * Check and error if SEPARATE_CODE_AND_RODATA is not set to 1 182bf1085dSKalyani Chidambaram ******************************************************************************/ 192bf1085dSKalyani Chidambaram #if !SEPARATE_CODE_AND_RODATA 202bf1085dSKalyani Chidambaram #error "SEPARATE_CODE_AND_RODATA should be set to 1" 212bf1085dSKalyani Chidambaram #endif 222bf1085dSKalyani Chidambaram 239c2eda01SVarun Wadekar /* 249c2eda01SVarun Wadekar * Platform binary types for linking 259c2eda01SVarun Wadekar */ 269c2eda01SVarun Wadekar #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 279c2eda01SVarun Wadekar #define PLATFORM_LINKER_ARCH aarch64 289c2eda01SVarun Wadekar 2942080d48SVarun Wadekar /* 3042080d48SVarun Wadekar * Platform binary types for linking 3142080d48SVarun Wadekar */ 3242080d48SVarun Wadekar #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 3342080d48SVarun Wadekar #define PLATFORM_LINKER_ARCH aarch64 3442080d48SVarun Wadekar 3508438e24SVarun Wadekar /******************************************************************************* 3608438e24SVarun Wadekar * Generic platform constants 3708438e24SVarun Wadekar ******************************************************************************/ 3808438e24SVarun Wadekar 3908438e24SVarun Wadekar /* Size of cacheable stacks */ 403d8256b2SMasahiro Yamada #ifdef IMAGE_BL31 4170cb692eSVarun Wadekar #define PLATFORM_STACK_SIZE U(0x400) 4208438e24SVarun Wadekar #endif 4308438e24SVarun Wadekar 4470cb692eSVarun Wadekar #define TEGRA_PRIMARY_CPU U(0x0) 4508438e24SVarun Wadekar 4671cb26eaSVarun Wadekar #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 4743ec35eeSVarun Wadekar #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 4843ec35eeSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER) 4971cb26eaSVarun Wadekar #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 509aaa8882SAnthony Zhou PLATFORM_CLUSTER_COUNT + U(1)) 5108438e24SVarun Wadekar 5208438e24SVarun Wadekar /******************************************************************************* 5308438e24SVarun Wadekar * Platform console related constants 5408438e24SVarun Wadekar ******************************************************************************/ 5570cb692eSVarun Wadekar #define TEGRA_CONSOLE_BAUDRATE U(115200) 56322e7c3eSHarvey Hsieh #define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000) 57322e7c3eSHarvey Hsieh #define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000) 5808438e24SVarun Wadekar 5908438e24SVarun Wadekar /******************************************************************************* 6008438e24SVarun Wadekar * Platform memory map related constants 6108438e24SVarun Wadekar ******************************************************************************/ 6208438e24SVarun Wadekar /* Size of trusted dram */ 6370cb692eSVarun Wadekar #define TZDRAM_SIZE U(0x00400000) 6408438e24SVarun Wadekar #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) 6508438e24SVarun Wadekar 6608438e24SVarun Wadekar /******************************************************************************* 6708438e24SVarun Wadekar * BL31 specific defines. 6808438e24SVarun Wadekar ******************************************************************************/ 6970cb692eSVarun Wadekar #define BL31_SIZE U(0x40000) 7008438e24SVarun Wadekar #define BL31_BASE TZDRAM_BASE 71dc7fdad2SVarun Wadekar #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) 72dc7fdad2SVarun Wadekar #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) 73dc7fdad2SVarun Wadekar #define BL32_LIMIT TZDRAM_END 7408438e24SVarun Wadekar 7508438e24SVarun Wadekar /******************************************************************************* 7608438e24SVarun Wadekar * Some data must be aligned on the biggest cache line size in the platform. 7708438e24SVarun Wadekar * This is known only to the platform as it might have a combination of 7808438e24SVarun Wadekar * integrated and external caches. 7908438e24SVarun Wadekar ******************************************************************************/ 8008438e24SVarun Wadekar #define CACHE_WRITEBACK_SHIFT 6 81636fcb0bSKalyani Chidambaram #define CACHE_WRITEBACK_GRANULE (0x40) /* (U(1) << CACHE_WRITEBACK_SHIFT) */ 8208438e24SVarun Wadekar 838d56e24bSVarun Wadekar /******************************************************************************* 848d56e24bSVarun Wadekar * Dummy macros to compile io_storage support 858d56e24bSVarun Wadekar ******************************************************************************/ 868d56e24bSVarun Wadekar #define MAX_IO_DEVICES U(0) 878d56e24bSVarun Wadekar #define MAX_IO_HANDLES U(0) 888d56e24bSVarun Wadekar 89adb20a17SVarun Wadekar /******************************************************************************* 90d886628dSVarun Wadekar * Platforms macros to support SDEI 91d886628dSVarun Wadekar ******************************************************************************/ 92d886628dSVarun Wadekar #define TEGRA_SDEI_SGI_PRIVATE U(8) 93d886628dSVarun Wadekar 94d886628dSVarun Wadekar /******************************************************************************* 95adb20a17SVarun Wadekar * Platform macros to support exception handling framework 96adb20a17SVarun Wadekar ******************************************************************************/ 97adb20a17SVarun Wadekar #define PLAT_PRI_BITS U(3) 98*8ca61538SDavid Pu #define PLAT_RAS_PRI U(0x10) 99d886628dSVarun Wadekar #define PLAT_SDEI_CRITICAL_PRI U(0x20) 100d886628dSVarun Wadekar #define PLAT_SDEI_NORMAL_PRI U(0x30) 101adb20a17SVarun Wadekar #define PLAT_TEGRA_WDT_PRIO U(0x40) 1022bf1085dSKalyani Chidambaram 103d886628dSVarun Wadekar /******************************************************************************* 104d886628dSVarun Wadekar * SDEI events 105d886628dSVarun Wadekar ******************************************************************************/ 106d886628dSVarun Wadekar /* SDEI dynamic private event numbers */ 107d886628dSVarun Wadekar #define TEGRA_SDEI_DP_EVENT_0 U(100) 108d886628dSVarun Wadekar #define TEGRA_SDEI_DP_EVENT_1 U(101) 109d886628dSVarun Wadekar #define TEGRA_SDEI_DP_EVENT_2 U(102) 110d886628dSVarun Wadekar 111d886628dSVarun Wadekar /* SDEI dynamic shared event numbers */ 112d886628dSVarun Wadekar #define TEGRA_SDEI_DS_EVENT_0 U(200) 113d886628dSVarun Wadekar #define TEGRA_SDEI_DS_EVENT_1 U(201) 114d886628dSVarun Wadekar #define TEGRA_SDEI_DS_EVENT_2 U(202) 115d886628dSVarun Wadekar 116d886628dSVarun Wadekar /* SDEI explicit events */ 117d886628dSVarun Wadekar #define TEGRA_SDEI_EP_EVENT_0 U(300) 118d886628dSVarun Wadekar #define TEGRA_SDEI_EP_EVENT_1 U(301) 119d886628dSVarun Wadekar #define TEGRA_SDEI_EP_EVENT_2 U(302) 120d886628dSVarun Wadekar #define TEGRA_SDEI_EP_EVENT_3 U(303) 121d886628dSVarun Wadekar #define TEGRA_SDEI_EP_EVENT_4 U(304) 122d886628dSVarun Wadekar #define TEGRA_SDEI_EP_EVENT_5 U(305) 123d886628dSVarun Wadekar #define TEGRA_SDEI_EP_EVENT_6 U(306) 124d886628dSVarun Wadekar #define TEGRA_SDEI_EP_EVENT_7 U(307) 125d886628dSVarun Wadekar #define TEGRA_SDEI_EP_EVENT_8 U(308) 126d886628dSVarun Wadekar #define TEGRA_SDEI_EP_EVENT_9 U(309) 127d886628dSVarun Wadekar #define TEGRA_SDEI_EP_EVENT_10 U(310) 128d886628dSVarun Wadekar #define TEGRA_SDEI_EP_EVENT_11 U(311) 129d886628dSVarun Wadekar 130c3cf06f1SAntonio Nino Diaz #endif /* PLATFORM_DEF_H */ 131