108438e24SVarun Wadekar /* 208438e24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 408438e24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 508438e24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 608438e24SVarun Wadekar * 708438e24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 808438e24SVarun Wadekar * list of conditions and the following disclaimer. 908438e24SVarun Wadekar * 1008438e24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 1108438e24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 1208438e24SVarun Wadekar * and/or other materials provided with the distribution. 1308438e24SVarun Wadekar * 1408438e24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 1508438e24SVarun Wadekar * to endorse or promote products derived from this software without specific 1608438e24SVarun Wadekar * prior written permission. 1708438e24SVarun Wadekar * 1808438e24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1908438e24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2008438e24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2108438e24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2208438e24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2308438e24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2408438e24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2508438e24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2608438e24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2708438e24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2808438e24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 2908438e24SVarun Wadekar */ 3008438e24SVarun Wadekar 3108438e24SVarun Wadekar #ifndef __PLATFORM_DEF_H__ 3208438e24SVarun Wadekar #define __PLATFORM_DEF_H__ 3308438e24SVarun Wadekar 3408438e24SVarun Wadekar #include <arch.h> 3508438e24SVarun Wadekar #include <common_def.h> 36*71cb26eaSVarun Wadekar #include <tegra_def.h> 3708438e24SVarun Wadekar 3808438e24SVarun Wadekar /******************************************************************************* 3908438e24SVarun Wadekar * Generic platform constants 4008438e24SVarun Wadekar ******************************************************************************/ 4108438e24SVarun Wadekar 4208438e24SVarun Wadekar /* Size of cacheable stacks */ 4308438e24SVarun Wadekar #if DEBUG_XLAT_TABLE 4408438e24SVarun Wadekar #define PLATFORM_STACK_SIZE 0x800 4508438e24SVarun Wadekar #elif IMAGE_BL31 4608438e24SVarun Wadekar #define PLATFORM_STACK_SIZE 0x400 4708438e24SVarun Wadekar #endif 4808438e24SVarun Wadekar 4908438e24SVarun Wadekar #define TEGRA_PRIMARY_CPU 0x0 5008438e24SVarun Wadekar 51*71cb26eaSVarun Wadekar #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 5243ec35eeSVarun Wadekar #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 5343ec35eeSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER) 54*71cb26eaSVarun Wadekar #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 5508438e24SVarun Wadekar PLATFORM_CLUSTER_COUNT + 1) 5608438e24SVarun Wadekar 5708438e24SVarun Wadekar /******************************************************************************* 58*71cb26eaSVarun Wadekar * Platform power states 59*71cb26eaSVarun Wadekar ******************************************************************************/ 60*71cb26eaSVarun Wadekar #define PLAT_MAX_RET_STATE 1 61*71cb26eaSVarun Wadekar #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1) 62*71cb26eaSVarun Wadekar 63*71cb26eaSVarun Wadekar /******************************************************************************* 6408438e24SVarun Wadekar * Platform console related constants 6508438e24SVarun Wadekar ******************************************************************************/ 6608438e24SVarun Wadekar #define TEGRA_CONSOLE_BAUDRATE 115200 6708438e24SVarun Wadekar #define TEGRA_BOOT_UART_CLK_IN_HZ 408000000 6808438e24SVarun Wadekar 6908438e24SVarun Wadekar /******************************************************************************* 7008438e24SVarun Wadekar * Platform memory map related constants 7108438e24SVarun Wadekar ******************************************************************************/ 7208438e24SVarun Wadekar /* Size of trusted dram */ 7308438e24SVarun Wadekar #define TZDRAM_SIZE 0x00400000 7408438e24SVarun Wadekar #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) 7508438e24SVarun Wadekar 7608438e24SVarun Wadekar /******************************************************************************* 7708438e24SVarun Wadekar * BL31 specific defines. 7808438e24SVarun Wadekar ******************************************************************************/ 79dc7fdad2SVarun Wadekar #define BL31_SIZE 0x20000 8008438e24SVarun Wadekar #define BL31_BASE TZDRAM_BASE 81dc7fdad2SVarun Wadekar #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) 82dc7fdad2SVarun Wadekar #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) 83dc7fdad2SVarun Wadekar #define BL32_LIMIT TZDRAM_END 8408438e24SVarun Wadekar 8508438e24SVarun Wadekar /******************************************************************************* 8608438e24SVarun Wadekar * Platform specific page table and MMU setup constants 8708438e24SVarun Wadekar ******************************************************************************/ 8808438e24SVarun Wadekar #define ADDR_SPACE_SIZE (1ull << 32) 8908438e24SVarun Wadekar #define MAX_XLAT_TABLES 3 9008438e24SVarun Wadekar #define MAX_MMAP_REGIONS 8 9108438e24SVarun Wadekar 9208438e24SVarun Wadekar /******************************************************************************* 9308438e24SVarun Wadekar * Some data must be aligned on the biggest cache line size in the platform. 9408438e24SVarun Wadekar * This is known only to the platform as it might have a combination of 9508438e24SVarun Wadekar * integrated and external caches. 9608438e24SVarun Wadekar ******************************************************************************/ 9708438e24SVarun Wadekar #define CACHE_WRITEBACK_SHIFT 6 9808438e24SVarun Wadekar #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 9908438e24SVarun Wadekar 10008438e24SVarun Wadekar #endif /* __PLATFORM_DEF_H__ */ 101