108438e24SVarun Wadekar /* 2c05a2197SVarun Wadekar * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 708438e24SVarun Wadekar #ifndef __PLATFORM_DEF_H__ 808438e24SVarun Wadekar #define __PLATFORM_DEF_H__ 908438e24SVarun Wadekar 1008438e24SVarun Wadekar #include <arch.h> 1108438e24SVarun Wadekar #include <common_def.h> 1271cb26eaSVarun Wadekar #include <tegra_def.h> 13*70cb692eSVarun Wadekar #include <utils_def.h> 1408438e24SVarun Wadekar 1508438e24SVarun Wadekar /******************************************************************************* 1608438e24SVarun Wadekar * Generic platform constants 1708438e24SVarun Wadekar ******************************************************************************/ 1808438e24SVarun Wadekar 1908438e24SVarun Wadekar /* Size of cacheable stacks */ 203d8256b2SMasahiro Yamada #ifdef IMAGE_BL31 21*70cb692eSVarun Wadekar #define PLATFORM_STACK_SIZE U(0x400) 2208438e24SVarun Wadekar #endif 2308438e24SVarun Wadekar 24*70cb692eSVarun Wadekar #define TEGRA_PRIMARY_CPU U(0x0) 2508438e24SVarun Wadekar 2671cb26eaSVarun Wadekar #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 2743ec35eeSVarun Wadekar #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 2843ec35eeSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER) 2971cb26eaSVarun Wadekar #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 3008438e24SVarun Wadekar PLATFORM_CLUSTER_COUNT + 1) 3108438e24SVarun Wadekar 3208438e24SVarun Wadekar /******************************************************************************* 3308438e24SVarun Wadekar * Platform console related constants 3408438e24SVarun Wadekar ******************************************************************************/ 35*70cb692eSVarun Wadekar #define TEGRA_CONSOLE_BAUDRATE U(115200) 36*70cb692eSVarun Wadekar #define TEGRA_BOOT_UART_CLK_IN_HZ U(408000000) 3708438e24SVarun Wadekar 3808438e24SVarun Wadekar /******************************************************************************* 3908438e24SVarun Wadekar * Platform memory map related constants 4008438e24SVarun Wadekar ******************************************************************************/ 4108438e24SVarun Wadekar /* Size of trusted dram */ 42*70cb692eSVarun Wadekar #define TZDRAM_SIZE U(0x00400000) 4308438e24SVarun Wadekar #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) 4408438e24SVarun Wadekar 4508438e24SVarun Wadekar /******************************************************************************* 4608438e24SVarun Wadekar * BL31 specific defines. 4708438e24SVarun Wadekar ******************************************************************************/ 48*70cb692eSVarun Wadekar #define BL31_SIZE U(0x40000) 4908438e24SVarun Wadekar #define BL31_BASE TZDRAM_BASE 50dc7fdad2SVarun Wadekar #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) 51dc7fdad2SVarun Wadekar #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) 52dc7fdad2SVarun Wadekar #define BL32_LIMIT TZDRAM_END 5308438e24SVarun Wadekar 5408438e24SVarun Wadekar /******************************************************************************* 5508438e24SVarun Wadekar * Platform specific page table and MMU setup constants 5608438e24SVarun Wadekar ******************************************************************************/ 57*70cb692eSVarun Wadekar #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) 58*70cb692eSVarun Wadekar #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) 5908438e24SVarun Wadekar 6008438e24SVarun Wadekar /******************************************************************************* 6108438e24SVarun Wadekar * Some data must be aligned on the biggest cache line size in the platform. 6208438e24SVarun Wadekar * This is known only to the platform as it might have a combination of 6308438e24SVarun Wadekar * integrated and external caches. 6408438e24SVarun Wadekar ******************************************************************************/ 6508438e24SVarun Wadekar #define CACHE_WRITEBACK_SHIFT 6 66*70cb692eSVarun Wadekar #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 6708438e24SVarun Wadekar 6808438e24SVarun Wadekar #endif /* __PLATFORM_DEF_H__ */ 69