108438e24SVarun Wadekar /* 21d11f73eSSteven Kao * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 7c3cf06f1SAntonio Nino Diaz #ifndef PLATFORM_DEF_H 8c3cf06f1SAntonio Nino Diaz #define PLATFORM_DEF_H 908438e24SVarun Wadekar 1008438e24SVarun Wadekar #include <arch.h> 1109d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 1209d40e0eSAntonio Nino Diaz 1371cb26eaSVarun Wadekar #include <tegra_def.h> 1408438e24SVarun Wadekar 15*2bf1085dSKalyani Chidambaram /******************************************************************************* 16*2bf1085dSKalyani Chidambaram * Check and error if SEPARATE_CODE_AND_RODATA is not set to 1 17*2bf1085dSKalyani Chidambaram ******************************************************************************/ 18*2bf1085dSKalyani Chidambaram #if !SEPARATE_CODE_AND_RODATA 19*2bf1085dSKalyani Chidambaram #error "SEPARATE_CODE_AND_RODATA should be set to 1" 20*2bf1085dSKalyani Chidambaram #endif 21*2bf1085dSKalyani Chidambaram 229c2eda01SVarun Wadekar /* 239c2eda01SVarun Wadekar * Platform binary types for linking 249c2eda01SVarun Wadekar */ 259c2eda01SVarun Wadekar #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 269c2eda01SVarun Wadekar #define PLATFORM_LINKER_ARCH aarch64 279c2eda01SVarun Wadekar 2808438e24SVarun Wadekar /******************************************************************************* 2908438e24SVarun Wadekar * Generic platform constants 3008438e24SVarun Wadekar ******************************************************************************/ 3108438e24SVarun Wadekar 3208438e24SVarun Wadekar /* Size of cacheable stacks */ 333d8256b2SMasahiro Yamada #ifdef IMAGE_BL31 3470cb692eSVarun Wadekar #define PLATFORM_STACK_SIZE U(0x400) 3508438e24SVarun Wadekar #endif 3608438e24SVarun Wadekar 3770cb692eSVarun Wadekar #define TEGRA_PRIMARY_CPU U(0x0) 3808438e24SVarun Wadekar 3971cb26eaSVarun Wadekar #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 4043ec35eeSVarun Wadekar #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 4143ec35eeSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER) 4271cb26eaSVarun Wadekar #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 4308438e24SVarun Wadekar PLATFORM_CLUSTER_COUNT + 1) 4408438e24SVarun Wadekar 4508438e24SVarun Wadekar /******************************************************************************* 4608438e24SVarun Wadekar * Platform console related constants 4708438e24SVarun Wadekar ******************************************************************************/ 4870cb692eSVarun Wadekar #define TEGRA_CONSOLE_BAUDRATE U(115200) 49322e7c3eSHarvey Hsieh #define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000) 50322e7c3eSHarvey Hsieh #define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000) 5108438e24SVarun Wadekar 5208438e24SVarun Wadekar /******************************************************************************* 5308438e24SVarun Wadekar * Platform memory map related constants 5408438e24SVarun Wadekar ******************************************************************************/ 5508438e24SVarun Wadekar /* Size of trusted dram */ 5670cb692eSVarun Wadekar #define TZDRAM_SIZE U(0x00400000) 5708438e24SVarun Wadekar #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) 5808438e24SVarun Wadekar 5908438e24SVarun Wadekar /******************************************************************************* 6008438e24SVarun Wadekar * BL31 specific defines. 6108438e24SVarun Wadekar ******************************************************************************/ 6270cb692eSVarun Wadekar #define BL31_SIZE U(0x40000) 6308438e24SVarun Wadekar #define BL31_BASE TZDRAM_BASE 64dc7fdad2SVarun Wadekar #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) 65dc7fdad2SVarun Wadekar #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) 66dc7fdad2SVarun Wadekar #define BL32_LIMIT TZDRAM_END 6708438e24SVarun Wadekar 6808438e24SVarun Wadekar /******************************************************************************* 6908438e24SVarun Wadekar * Some data must be aligned on the biggest cache line size in the platform. 7008438e24SVarun Wadekar * This is known only to the platform as it might have a combination of 7108438e24SVarun Wadekar * integrated and external caches. 7208438e24SVarun Wadekar ******************************************************************************/ 7308438e24SVarun Wadekar #define CACHE_WRITEBACK_SHIFT 6 74636fcb0bSKalyani Chidambaram #define CACHE_WRITEBACK_GRANULE (0x40) /* (U(1) << CACHE_WRITEBACK_SHIFT) */ 7508438e24SVarun Wadekar 768d56e24bSVarun Wadekar /******************************************************************************* 778d56e24bSVarun Wadekar * Dummy macros to compile io_storage support 788d56e24bSVarun Wadekar ******************************************************************************/ 798d56e24bSVarun Wadekar #define MAX_IO_DEVICES U(0) 808d56e24bSVarun Wadekar #define MAX_IO_HANDLES U(0) 818d56e24bSVarun Wadekar 82*2bf1085dSKalyani Chidambaram 83c3cf06f1SAntonio Nino Diaz #endif /* PLATFORM_DEF_H */ 84