108438e24SVarun Wadekar /* 2*1d11f73eSSteven Kao * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 7c3cf06f1SAntonio Nino Diaz #ifndef PLATFORM_DEF_H 8c3cf06f1SAntonio Nino Diaz #define PLATFORM_DEF_H 908438e24SVarun Wadekar 1008438e24SVarun Wadekar #include <arch.h> 1109d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 1209d40e0eSAntonio Nino Diaz #include <plat/common/common_def.h> 1309d40e0eSAntonio Nino Diaz 1471cb26eaSVarun Wadekar #include <tegra_def.h> 1508438e24SVarun Wadekar 1608438e24SVarun Wadekar /******************************************************************************* 1708438e24SVarun Wadekar * Generic platform constants 1808438e24SVarun Wadekar ******************************************************************************/ 1908438e24SVarun Wadekar 2008438e24SVarun Wadekar /* Size of cacheable stacks */ 213d8256b2SMasahiro Yamada #ifdef IMAGE_BL31 2270cb692eSVarun Wadekar #define PLATFORM_STACK_SIZE U(0x400) 2308438e24SVarun Wadekar #endif 2408438e24SVarun Wadekar 2570cb692eSVarun Wadekar #define TEGRA_PRIMARY_CPU U(0x0) 2608438e24SVarun Wadekar 2771cb26eaSVarun Wadekar #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 2843ec35eeSVarun Wadekar #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 2943ec35eeSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER) 3071cb26eaSVarun Wadekar #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 3108438e24SVarun Wadekar PLATFORM_CLUSTER_COUNT + 1) 3208438e24SVarun Wadekar 3308438e24SVarun Wadekar /******************************************************************************* 3408438e24SVarun Wadekar * Platform console related constants 3508438e24SVarun Wadekar ******************************************************************************/ 3670cb692eSVarun Wadekar #define TEGRA_CONSOLE_BAUDRATE U(115200) 37322e7c3eSHarvey Hsieh #define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000) 38322e7c3eSHarvey Hsieh #define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000) 3908438e24SVarun Wadekar 4008438e24SVarun Wadekar /******************************************************************************* 4108438e24SVarun Wadekar * Platform memory map related constants 4208438e24SVarun Wadekar ******************************************************************************/ 4308438e24SVarun Wadekar /* Size of trusted dram */ 4470cb692eSVarun Wadekar #define TZDRAM_SIZE U(0x00400000) 4508438e24SVarun Wadekar #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) 4608438e24SVarun Wadekar 4708438e24SVarun Wadekar /******************************************************************************* 4808438e24SVarun Wadekar * BL31 specific defines. 4908438e24SVarun Wadekar ******************************************************************************/ 5070cb692eSVarun Wadekar #define BL31_SIZE U(0x40000) 5108438e24SVarun Wadekar #define BL31_BASE TZDRAM_BASE 52dc7fdad2SVarun Wadekar #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) 53dc7fdad2SVarun Wadekar #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) 54dc7fdad2SVarun Wadekar #define BL32_LIMIT TZDRAM_END 5508438e24SVarun Wadekar 5608438e24SVarun Wadekar /******************************************************************************* 5708438e24SVarun Wadekar * Some data must be aligned on the biggest cache line size in the platform. 5808438e24SVarun Wadekar * This is known only to the platform as it might have a combination of 5908438e24SVarun Wadekar * integrated and external caches. 6008438e24SVarun Wadekar ******************************************************************************/ 6108438e24SVarun Wadekar #define CACHE_WRITEBACK_SHIFT 6 6270cb692eSVarun Wadekar #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 6308438e24SVarun Wadekar 64c3cf06f1SAntonio Nino Diaz #endif /* PLATFORM_DEF_H */ 65