1*08438e24SVarun Wadekar /* 2*08438e24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*08438e24SVarun Wadekar * 4*08438e24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*08438e24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*08438e24SVarun Wadekar * 7*08438e24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*08438e24SVarun Wadekar * list of conditions and the following disclaimer. 9*08438e24SVarun Wadekar * 10*08438e24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*08438e24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*08438e24SVarun Wadekar * and/or other materials provided with the distribution. 13*08438e24SVarun Wadekar * 14*08438e24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*08438e24SVarun Wadekar * to endorse or promote products derived from this software without specific 16*08438e24SVarun Wadekar * prior written permission. 17*08438e24SVarun Wadekar * 18*08438e24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*08438e24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*08438e24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*08438e24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*08438e24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*08438e24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*08438e24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*08438e24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*08438e24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*08438e24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*08438e24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*08438e24SVarun Wadekar */ 30*08438e24SVarun Wadekar 31*08438e24SVarun Wadekar #ifndef __PLATFORM_DEF_H__ 32*08438e24SVarun Wadekar #define __PLATFORM_DEF_H__ 33*08438e24SVarun Wadekar 34*08438e24SVarun Wadekar #include <arch.h> 35*08438e24SVarun Wadekar #include <common_def.h> 36*08438e24SVarun Wadekar 37*08438e24SVarun Wadekar /******************************************************************************* 38*08438e24SVarun Wadekar * Generic platform constants 39*08438e24SVarun Wadekar ******************************************************************************/ 40*08438e24SVarun Wadekar 41*08438e24SVarun Wadekar /* Size of cacheable stacks */ 42*08438e24SVarun Wadekar #if DEBUG_XLAT_TABLE 43*08438e24SVarun Wadekar #define PLATFORM_STACK_SIZE 0x800 44*08438e24SVarun Wadekar #elif IMAGE_BL31 45*08438e24SVarun Wadekar #define PLATFORM_STACK_SIZE 0x400 46*08438e24SVarun Wadekar #endif 47*08438e24SVarun Wadekar 48*08438e24SVarun Wadekar #define TEGRA_PRIMARY_CPU 0x0 49*08438e24SVarun Wadekar 50*08438e24SVarun Wadekar #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 51*08438e24SVarun Wadekar #define PLATFORM_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 52*08438e24SVarun Wadekar #define PLATFORM_NUM_AFFS ((PLATFORM_CLUSTER_COUNT * \ 53*08438e24SVarun Wadekar PLATFORM_CORE_COUNT) + \ 54*08438e24SVarun Wadekar PLATFORM_CLUSTER_COUNT + 1) 55*08438e24SVarun Wadekar 56*08438e24SVarun Wadekar /******************************************************************************* 57*08438e24SVarun Wadekar * Platform console related constants 58*08438e24SVarun Wadekar ******************************************************************************/ 59*08438e24SVarun Wadekar #define TEGRA_CONSOLE_BAUDRATE 115200 60*08438e24SVarun Wadekar #define TEGRA_BOOT_UART_CLK_IN_HZ 408000000 61*08438e24SVarun Wadekar 62*08438e24SVarun Wadekar /******************************************************************************* 63*08438e24SVarun Wadekar * Platform memory map related constants 64*08438e24SVarun Wadekar ******************************************************************************/ 65*08438e24SVarun Wadekar /* Size of trusted dram */ 66*08438e24SVarun Wadekar #define TZDRAM_SIZE 0x00400000 67*08438e24SVarun Wadekar #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) 68*08438e24SVarun Wadekar 69*08438e24SVarun Wadekar /******************************************************************************* 70*08438e24SVarun Wadekar * BL31 specific defines. 71*08438e24SVarun Wadekar ******************************************************************************/ 72*08438e24SVarun Wadekar #define BL31_BASE TZDRAM_BASE 73*08438e24SVarun Wadekar #define BL31_LIMIT (TZDRAM_BASE + 0x11FFF) 74*08438e24SVarun Wadekar 75*08438e24SVarun Wadekar /******************************************************************************* 76*08438e24SVarun Wadekar * Platform specific page table and MMU setup constants 77*08438e24SVarun Wadekar ******************************************************************************/ 78*08438e24SVarun Wadekar #define ADDR_SPACE_SIZE (1ull << 32) 79*08438e24SVarun Wadekar #define MAX_XLAT_TABLES 3 80*08438e24SVarun Wadekar #define MAX_MMAP_REGIONS 8 81*08438e24SVarun Wadekar 82*08438e24SVarun Wadekar /******************************************************************************* 83*08438e24SVarun Wadekar * Some data must be aligned on the biggest cache line size in the platform. 84*08438e24SVarun Wadekar * This is known only to the platform as it might have a combination of 85*08438e24SVarun Wadekar * integrated and external caches. 86*08438e24SVarun Wadekar ******************************************************************************/ 87*08438e24SVarun Wadekar #define CACHE_WRITEBACK_SHIFT 6 88*08438e24SVarun Wadekar #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 89*08438e24SVarun Wadekar 90*08438e24SVarun Wadekar #endif /* __PLATFORM_DEF_H__ */ 91