1/* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#ifndef __PLAT_MACROS_S__ 32#define __PLAT_MACROS_S__ 33 34#include <gic_v2.h> 35#include <tegra_def.h> 36 37.section .rodata.gic_reg_name, "aS" 38gicc_regs: 39 .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 40gicd_pend_reg: 41 .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" 42newline: 43 .asciz "\n" 44spacer: 45 .asciz ":\t\t0x" 46 47/* --------------------------------------------- 48 * The below macro prints out relevant GIC 49 * registers whenever an unhandled exception is 50 * taken in BL31. 51 * --------------------------------------------- 52 */ 53.macro plat_print_gic_regs 54 mov_imm x16, TEGRA_GICC_BASE 55 cbz x16, 1f 56 /* gicc base address is now in x16 */ 57 adr x6, gicc_regs /* Load the gicc reg list to x6 */ 58 /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 59 ldr w8, [x16, #GICC_HPPIR] 60 ldr w9, [x16, #GICC_AHPPIR] 61 ldr w10, [x16, #GICC_CTLR] 62 /* Store to the crash buf and print to cosole */ 63 bl str_in_crash_buf_print 64 65 /* Print the GICD_ISPENDR regs */ 66 add x7, x16, #GICD_ISPENDR 67 adr x4, gicd_pend_reg 68 bl asm_print_str 692: 70 sub x4, x7, x16 71 cmp x4, #0x280 72 b.eq 1f 73 bl asm_print_hex 74 adr x4, spacer 75 bl asm_print_str 76 ldr x4, [x7], #8 77 bl asm_print_hex 78 adr x4, newline 79 bl asm_print_str 80 b 2b 811: 82.endm 83 84/* ------------------------------------------------ 85 * The below required platform porting macro prints 86 * out relevant interconnect registers whenever an 87 * unhandled exception is taken in BL3-1. 88 * ------------------------------------------------ 89 */ 90.macro plat_print_interconnect_regs 91 nop 92.endm 93 94#endif /* __PLAT_MACROS_S__ */ 95