108438e24SVarun Wadekar/* 208438e24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 708438e24SVarun Wadekar#ifndef __PLAT_MACROS_S__ 808438e24SVarun Wadekar#define __PLAT_MACROS_S__ 908438e24SVarun Wadekar 1008438e24SVarun Wadekar#include <gic_v2.h> 1108438e24SVarun Wadekar#include <tegra_def.h> 1208438e24SVarun Wadekar 1308438e24SVarun Wadekar.section .rodata.gic_reg_name, "aS" 1408438e24SVarun Wadekargicc_regs: 1508438e24SVarun Wadekar .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 1608438e24SVarun Wadekargicd_pend_reg: 1708438e24SVarun Wadekar .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" 1808438e24SVarun Wadekarnewline: 1908438e24SVarun Wadekar .asciz "\n" 2008438e24SVarun Wadekarspacer: 2108438e24SVarun Wadekar .asciz ":\t\t0x" 2208438e24SVarun Wadekar 2308438e24SVarun Wadekar/* --------------------------------------------- 2408438e24SVarun Wadekar * The below macro prints out relevant GIC 2508438e24SVarun Wadekar * registers whenever an unhandled exception is 2608438e24SVarun Wadekar * taken in BL31. 2708438e24SVarun Wadekar * --------------------------------------------- 2808438e24SVarun Wadekar */ 299ff67fa6SGerald Lejeune.macro plat_crash_print_regs 3008438e24SVarun Wadekar mov_imm x16, TEGRA_GICC_BASE 3123cd470fSVarun Wadekar 3208438e24SVarun Wadekar /* gicc base address is now in x16 */ 3308438e24SVarun Wadekar adr x6, gicc_regs /* Load the gicc reg list to x6 */ 3408438e24SVarun Wadekar /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 3508438e24SVarun Wadekar ldr w8, [x16, #GICC_HPPIR] 3608438e24SVarun Wadekar ldr w9, [x16, #GICC_AHPPIR] 3708438e24SVarun Wadekar ldr w10, [x16, #GICC_CTLR] 3808438e24SVarun Wadekar /* Store to the crash buf and print to cosole */ 3908438e24SVarun Wadekar bl str_in_crash_buf_print 4008438e24SVarun Wadekar 4108438e24SVarun Wadekar /* Print the GICD_ISPENDR regs */ 4223cd470fSVarun Wadekar mov_imm x16, TEGRA_GICD_BASE 4308438e24SVarun Wadekar add x7, x16, #GICD_ISPENDR 4408438e24SVarun Wadekar adr x4, gicd_pend_reg 4508438e24SVarun Wadekar bl asm_print_str 4608438e24SVarun Wadekar2: 4708438e24SVarun Wadekar sub x4, x7, x16 4808438e24SVarun Wadekar cmp x4, #0x280 4908438e24SVarun Wadekar b.eq 1f 5008438e24SVarun Wadekar bl asm_print_hex 5108438e24SVarun Wadekar adr x4, spacer 5208438e24SVarun Wadekar bl asm_print_str 5308438e24SVarun Wadekar ldr x4, [x7], #8 5408438e24SVarun Wadekar bl asm_print_hex 5508438e24SVarun Wadekar adr x4, newline 5608438e24SVarun Wadekar bl asm_print_str 5708438e24SVarun Wadekar b 2b 5808438e24SVarun Wadekar1: 5908438e24SVarun Wadekar.endm 6008438e24SVarun Wadekar 6108438e24SVarun Wadekar#endif /* __PLAT_MACROS_S__ */ 62