108438e24SVarun Wadekar/* 208438e24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 408438e24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 508438e24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 608438e24SVarun Wadekar * 708438e24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 808438e24SVarun Wadekar * list of conditions and the following disclaimer. 908438e24SVarun Wadekar * 1008438e24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 1108438e24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 1208438e24SVarun Wadekar * and/or other materials provided with the distribution. 1308438e24SVarun Wadekar * 1408438e24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 1508438e24SVarun Wadekar * to endorse or promote products derived from this software without specific 1608438e24SVarun Wadekar * prior written permission. 1708438e24SVarun Wadekar * 1808438e24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1908438e24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2008438e24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2108438e24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2208438e24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2308438e24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2408438e24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2508438e24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2608438e24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2708438e24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2808438e24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 2908438e24SVarun Wadekar */ 3008438e24SVarun Wadekar 3108438e24SVarun Wadekar#ifndef __PLAT_MACROS_S__ 3208438e24SVarun Wadekar#define __PLAT_MACROS_S__ 3308438e24SVarun Wadekar 3408438e24SVarun Wadekar#include <gic_v2.h> 3508438e24SVarun Wadekar#include <tegra_def.h> 3608438e24SVarun Wadekar 3708438e24SVarun Wadekar.section .rodata.gic_reg_name, "aS" 3808438e24SVarun Wadekargicc_regs: 3908438e24SVarun Wadekar .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 4008438e24SVarun Wadekargicd_pend_reg: 4108438e24SVarun Wadekar .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" 4208438e24SVarun Wadekarnewline: 4308438e24SVarun Wadekar .asciz "\n" 4408438e24SVarun Wadekarspacer: 4508438e24SVarun Wadekar .asciz ":\t\t0x" 4608438e24SVarun Wadekar 4708438e24SVarun Wadekar/* --------------------------------------------- 4808438e24SVarun Wadekar * The below macro prints out relevant GIC 4908438e24SVarun Wadekar * registers whenever an unhandled exception is 5008438e24SVarun Wadekar * taken in BL31. 5108438e24SVarun Wadekar * --------------------------------------------- 5208438e24SVarun Wadekar */ 539ff67fa6SGerald Lejeune.macro plat_crash_print_regs 5408438e24SVarun Wadekar mov_imm x16, TEGRA_GICC_BASE 55*23cd470fSVarun Wadekar 5608438e24SVarun Wadekar /* gicc base address is now in x16 */ 5708438e24SVarun Wadekar adr x6, gicc_regs /* Load the gicc reg list to x6 */ 5808438e24SVarun Wadekar /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 5908438e24SVarun Wadekar ldr w8, [x16, #GICC_HPPIR] 6008438e24SVarun Wadekar ldr w9, [x16, #GICC_AHPPIR] 6108438e24SVarun Wadekar ldr w10, [x16, #GICC_CTLR] 6208438e24SVarun Wadekar /* Store to the crash buf and print to cosole */ 6308438e24SVarun Wadekar bl str_in_crash_buf_print 6408438e24SVarun Wadekar 6508438e24SVarun Wadekar /* Print the GICD_ISPENDR regs */ 66*23cd470fSVarun Wadekar mov_imm x16, TEGRA_GICD_BASE 6708438e24SVarun Wadekar add x7, x16, #GICD_ISPENDR 6808438e24SVarun Wadekar adr x4, gicd_pend_reg 6908438e24SVarun Wadekar bl asm_print_str 7008438e24SVarun Wadekar2: 7108438e24SVarun Wadekar sub x4, x7, x16 7208438e24SVarun Wadekar cmp x4, #0x280 7308438e24SVarun Wadekar b.eq 1f 7408438e24SVarun Wadekar bl asm_print_hex 7508438e24SVarun Wadekar adr x4, spacer 7608438e24SVarun Wadekar bl asm_print_str 7708438e24SVarun Wadekar ldr x4, [x7], #8 7808438e24SVarun Wadekar bl asm_print_hex 7908438e24SVarun Wadekar adr x4, newline 8008438e24SVarun Wadekar bl asm_print_str 8108438e24SVarun Wadekar b 2b 8208438e24SVarun Wadekar1: 8308438e24SVarun Wadekar.endm 8408438e24SVarun Wadekar 8508438e24SVarun Wadekar#endif /* __PLAT_MACROS_S__ */ 86