1*08438e24SVarun Wadekar/* 2*08438e24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*08438e24SVarun Wadekar * 4*08438e24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*08438e24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*08438e24SVarun Wadekar * 7*08438e24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*08438e24SVarun Wadekar * list of conditions and the following disclaimer. 9*08438e24SVarun Wadekar * 10*08438e24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*08438e24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*08438e24SVarun Wadekar * and/or other materials provided with the distribution. 13*08438e24SVarun Wadekar * 14*08438e24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*08438e24SVarun Wadekar * to endorse or promote products derived from this software without specific 16*08438e24SVarun Wadekar * prior written permission. 17*08438e24SVarun Wadekar * 18*08438e24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*08438e24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*08438e24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*08438e24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*08438e24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*08438e24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*08438e24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*08438e24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*08438e24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*08438e24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*08438e24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*08438e24SVarun Wadekar */ 30*08438e24SVarun Wadekar 31*08438e24SVarun Wadekar#ifndef __PLAT_MACROS_S__ 32*08438e24SVarun Wadekar#define __PLAT_MACROS_S__ 33*08438e24SVarun Wadekar 34*08438e24SVarun Wadekar#include <gic_v2.h> 35*08438e24SVarun Wadekar#include <tegra_def.h> 36*08438e24SVarun Wadekar 37*08438e24SVarun Wadekar.section .rodata.gic_reg_name, "aS" 38*08438e24SVarun Wadekargicc_regs: 39*08438e24SVarun Wadekar .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 40*08438e24SVarun Wadekargicd_pend_reg: 41*08438e24SVarun Wadekar .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" 42*08438e24SVarun Wadekarnewline: 43*08438e24SVarun Wadekar .asciz "\n" 44*08438e24SVarun Wadekarspacer: 45*08438e24SVarun Wadekar .asciz ":\t\t0x" 46*08438e24SVarun Wadekar 47*08438e24SVarun Wadekar/* --------------------------------------------- 48*08438e24SVarun Wadekar * The below macro prints out relevant GIC 49*08438e24SVarun Wadekar * registers whenever an unhandled exception is 50*08438e24SVarun Wadekar * taken in BL31. 51*08438e24SVarun Wadekar * --------------------------------------------- 52*08438e24SVarun Wadekar */ 53*08438e24SVarun Wadekar.macro plat_print_gic_regs 54*08438e24SVarun Wadekar mov_imm x16, TEGRA_GICC_BASE 55*08438e24SVarun Wadekar cbz x16, 1f 56*08438e24SVarun Wadekar /* gicc base address is now in x16 */ 57*08438e24SVarun Wadekar adr x6, gicc_regs /* Load the gicc reg list to x6 */ 58*08438e24SVarun Wadekar /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 59*08438e24SVarun Wadekar ldr w8, [x16, #GICC_HPPIR] 60*08438e24SVarun Wadekar ldr w9, [x16, #GICC_AHPPIR] 61*08438e24SVarun Wadekar ldr w10, [x16, #GICC_CTLR] 62*08438e24SVarun Wadekar /* Store to the crash buf and print to cosole */ 63*08438e24SVarun Wadekar bl str_in_crash_buf_print 64*08438e24SVarun Wadekar 65*08438e24SVarun Wadekar /* Print the GICD_ISPENDR regs */ 66*08438e24SVarun Wadekar add x7, x16, #GICD_ISPENDR 67*08438e24SVarun Wadekar adr x4, gicd_pend_reg 68*08438e24SVarun Wadekar bl asm_print_str 69*08438e24SVarun Wadekar2: 70*08438e24SVarun Wadekar sub x4, x7, x16 71*08438e24SVarun Wadekar cmp x4, #0x280 72*08438e24SVarun Wadekar b.eq 1f 73*08438e24SVarun Wadekar bl asm_print_hex 74*08438e24SVarun Wadekar adr x4, spacer 75*08438e24SVarun Wadekar bl asm_print_str 76*08438e24SVarun Wadekar ldr x4, [x7], #8 77*08438e24SVarun Wadekar bl asm_print_hex 78*08438e24SVarun Wadekar adr x4, newline 79*08438e24SVarun Wadekar bl asm_print_str 80*08438e24SVarun Wadekar b 2b 81*08438e24SVarun Wadekar1: 82*08438e24SVarun Wadekar.endm 83*08438e24SVarun Wadekar 84*08438e24SVarun Wadekar/* ------------------------------------------------ 85*08438e24SVarun Wadekar * The below required platform porting macro prints 86*08438e24SVarun Wadekar * out relevant interconnect registers whenever an 87*08438e24SVarun Wadekar * unhandled exception is taken in BL3-1. 88*08438e24SVarun Wadekar * ------------------------------------------------ 89*08438e24SVarun Wadekar */ 90*08438e24SVarun Wadekar.macro plat_print_interconnect_regs 91*08438e24SVarun Wadekar nop 92*08438e24SVarun Wadekar.endm 93*08438e24SVarun Wadekar 94*08438e24SVarun Wadekar#endif /* __PLAT_MACROS_S__ */ 95