1*80c50eeaSVarun Wadekar /* 2*80c50eeaSVarun Wadekar * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*80c50eeaSVarun Wadekar * 4*80c50eeaSVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5*80c50eeaSVarun Wadekar */ 6*80c50eeaSVarun Wadekar 7*80c50eeaSVarun Wadekar #ifndef __TEGRA_GIC_H__ 8*80c50eeaSVarun Wadekar #define __TEGRA_GIC_H__ 9*80c50eeaSVarun Wadekar 10*80c50eeaSVarun Wadekar #include <interrupt_props.h> 11*80c50eeaSVarun Wadekar 12*80c50eeaSVarun Wadekar /******************************************************************************* 13*80c50eeaSVarun Wadekar * Per-CPU struct describing FIQ state to be stored 14*80c50eeaSVarun Wadekar ******************************************************************************/ 15*80c50eeaSVarun Wadekar typedef struct pcpu_fiq_state { 16*80c50eeaSVarun Wadekar uint64_t elr_el3; 17*80c50eeaSVarun Wadekar uint64_t spsr_el3; 18*80c50eeaSVarun Wadekar } pcpu_fiq_state_t; 19*80c50eeaSVarun Wadekar 20*80c50eeaSVarun Wadekar /******************************************************************************* 21*80c50eeaSVarun Wadekar * Fucntion declarations 22*80c50eeaSVarun Wadekar ******************************************************************************/ 23*80c50eeaSVarun Wadekar void tegra_gic_cpuif_deactivate(void); 24*80c50eeaSVarun Wadekar void tegra_gic_init(void); 25*80c50eeaSVarun Wadekar void tegra_gic_pcpu_init(void); 26*80c50eeaSVarun Wadekar void tegra_gic_setup(const interrupt_prop_t *interrupt_props, 27*80c50eeaSVarun Wadekar unsigned int interrupt_props_num); 28*80c50eeaSVarun Wadekar 29*80c50eeaSVarun Wadekar #endif /* __TEGRA_GIC_H__ */ 30