1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SMMU_H 9 #define SMMU_H 10 11 #include <lib/mmio.h> 12 13 #include <memctrl_v2.h> 14 #include <tegra_def.h> 15 16 #define SMMU_CBn_ACTLR (0x4U) 17 18 /******************************************************************************* 19 * SMMU Global Secure Aux. Configuration Register 20 ******************************************************************************/ 21 #define SMMU_GSR0_SECURE_ACR 0x10U 22 #define SMMU_GNSR_ACR (SMMU_GSR0_SECURE_ACR + 0x400U) 23 #define SMMU_GSR0_PGSIZE_SHIFT 16U 24 #define SMMU_GSR0_PGSIZE_4K (0U << SMMU_GSR0_PGSIZE_SHIFT) 25 #define SMMU_GSR0_PGSIZE_64K (1U << SMMU_GSR0_PGSIZE_SHIFT) 26 #define SMMU_ACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U) 27 #define SMMU_GSR0_PER (0x20200U) 28 29 /******************************************************************************* 30 * SMMU Global Aux. Control Register 31 ******************************************************************************/ 32 #define SMMU_CBn_ACTLR_CPRE_BIT (1ULL << 1U) 33 34 /* SMMU IDs currently supported by the driver */ 35 enum { 36 TEGRA_SMMU0 = 0U, 37 TEGRA_SMMU1 = 1U, 38 TEGRA_SMMU2 = 2U 39 }; 40 41 static inline uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off) 42 { 43 uint32_t ret = 0U; 44 45 #if defined(TEGRA_SMMU0_BASE) 46 if (smmu_id == TEGRA_SMMU0) { 47 ret = mmio_read_32(TEGRA_SMMU0_BASE + (uint64_t)off); 48 } 49 #endif 50 51 #if defined(TEGRA_SMMU1_BASE) 52 if (smmu_id == TEGRA_SMMU1) { 53 ret = mmio_read_32(TEGRA_SMMU1_BASE + (uint64_t)off); 54 } 55 #endif 56 57 #if defined(TEGRA_SMMU2_BASE) 58 if (smmu_id == TEGRA_SMMU2) { 59 ret = mmio_read_32(TEGRA_SMMU2_BASE + (uint64_t)off); 60 } 61 #endif 62 63 return ret; 64 } 65 66 static inline void tegra_smmu_write_32(uint32_t smmu_id, 67 uint32_t off, uint32_t val) 68 { 69 #if defined(TEGRA_SMMU0_BASE) 70 if (smmu_id == TEGRA_SMMU0) { 71 mmio_write_32(TEGRA_SMMU0_BASE + (uint64_t)off, val); 72 } 73 #endif 74 75 #if defined(TEGRA_SMMU1_BASE) 76 if (smmu_id == TEGRA_SMMU1) { 77 mmio_write_32(TEGRA_SMMU1_BASE + (uint64_t)off, val); 78 } 79 #endif 80 81 #if defined(TEGRA_SMMU2_BASE) 82 if (smmu_id == TEGRA_SMMU2) { 83 mmio_write_32(TEGRA_SMMU2_BASE + (uint64_t)off, val); 84 } 85 #endif 86 } 87 88 void tegra_smmu_init(void); 89 uint32_t plat_get_num_smmu_devices(void); 90 91 #endif /* SMMU_H */ 92