14122151fSVarun Wadekar /* 206803cfdSPritesh Raithatha * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3*a391d494SPritesh Raithatha * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 44122151fSVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 64122151fSVarun Wadekar */ 74122151fSVarun Wadekar 8c3cf06f1SAntonio Nino Diaz #ifndef SMMU_H 9c3cf06f1SAntonio Nino Diaz #define SMMU_H 104122151fSVarun Wadekar 1109d40e0eSAntonio Nino Diaz #include <lib/mmio.h> 1209d40e0eSAntonio Nino Diaz 1306803cfdSPritesh Raithatha #include <memctrl_v2.h> 144122151fSVarun Wadekar #include <tegra_def.h> 154122151fSVarun Wadekar 1650e91633SAnthony Zhou #define SMMU_CBn_ACTLR (0x4U) 174122151fSVarun Wadekar 184122151fSVarun Wadekar /******************************************************************************* 194122151fSVarun Wadekar * SMMU Global Secure Aux. Configuration Register 204122151fSVarun Wadekar ******************************************************************************/ 2150e91633SAnthony Zhou #define SMMU_GSR0_SECURE_ACR 0x10U 2250e91633SAnthony Zhou #define SMMU_GNSR_ACR (SMMU_GSR0_SECURE_ACR + 0x400U) 2350e91633SAnthony Zhou #define SMMU_GSR0_PGSIZE_SHIFT 16U 2450e91633SAnthony Zhou #define SMMU_GSR0_PGSIZE_4K (0U << SMMU_GSR0_PGSIZE_SHIFT) 2550e91633SAnthony Zhou #define SMMU_GSR0_PGSIZE_64K (1U << SMMU_GSR0_PGSIZE_SHIFT) 2650e91633SAnthony Zhou #define SMMU_ACR_CACHE_LOCK_ENABLE_BIT (1U << 26) 27698f4250SVarun Wadekar 28698f4250SVarun Wadekar /******************************************************************************* 29698f4250SVarun Wadekar * SMMU Global Aux. Control Register 30698f4250SVarun Wadekar ******************************************************************************/ 31aa64c5fbSAnthony Zhou #define SMMU_CBn_ACTLR_CPRE_BIT (1ULL << 1U) 324122151fSVarun Wadekar 334122151fSVarun Wadekar void tegra_smmu_init(void); 34bc5a86f7SSteven Kao uint32_t plat_get_num_smmu_devices(void); 354122151fSVarun Wadekar 36c3cf06f1SAntonio Nino Diaz #endif /* SMMU_H */ 37