14122151fSVarun Wadekar /*
206803cfdSPritesh Raithatha * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
3a391d494SPritesh Raithatha * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
44122151fSVarun Wadekar *
582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause
64122151fSVarun Wadekar */
74122151fSVarun Wadekar
8c3cf06f1SAntonio Nino Diaz #ifndef SMMU_H
9c3cf06f1SAntonio Nino Diaz #define SMMU_H
104122151fSVarun Wadekar
1109d40e0eSAntonio Nino Diaz #include <lib/mmio.h>
1209d40e0eSAntonio Nino Diaz
1306803cfdSPritesh Raithatha #include <memctrl_v2.h>
144122151fSVarun Wadekar #include <tegra_def.h>
154122151fSVarun Wadekar
1650e91633SAnthony Zhou #define SMMU_CBn_ACTLR (0x4U)
174122151fSVarun Wadekar
184122151fSVarun Wadekar /*******************************************************************************
194122151fSVarun Wadekar * SMMU Global Secure Aux. Configuration Register
204122151fSVarun Wadekar ******************************************************************************/
2150e91633SAnthony Zhou #define SMMU_GSR0_SECURE_ACR 0x10U
2250e91633SAnthony Zhou #define SMMU_GNSR_ACR (SMMU_GSR0_SECURE_ACR + 0x400U)
2350e91633SAnthony Zhou #define SMMU_GSR0_PGSIZE_SHIFT 16U
2450e91633SAnthony Zhou #define SMMU_GSR0_PGSIZE_4K (0U << SMMU_GSR0_PGSIZE_SHIFT)
2550e91633SAnthony Zhou #define SMMU_GSR0_PGSIZE_64K (1U << SMMU_GSR0_PGSIZE_SHIFT)
2691dd7eddSVarun Wadekar #define SMMU_ACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U)
2791dd7eddSVarun Wadekar #define SMMU_GSR0_PER (0x20200U)
28698f4250SVarun Wadekar
29698f4250SVarun Wadekar /*******************************************************************************
30698f4250SVarun Wadekar * SMMU Global Aux. Control Register
31698f4250SVarun Wadekar ******************************************************************************/
32aa64c5fbSAnthony Zhou #define SMMU_CBn_ACTLR_CPRE_BIT (1ULL << 1U)
334122151fSVarun Wadekar
3491dd7eddSVarun Wadekar /* SMMU IDs currently supported by the driver */
3591dd7eddSVarun Wadekar enum {
3691dd7eddSVarun Wadekar TEGRA_SMMU0 = 0U,
3791dd7eddSVarun Wadekar TEGRA_SMMU1 = 1U,
3891dd7eddSVarun Wadekar TEGRA_SMMU2 = 2U
3991dd7eddSVarun Wadekar };
4091dd7eddSVarun Wadekar
tegra_smmu_read_32(uint32_t smmu_id,uint32_t off)4191dd7eddSVarun Wadekar static inline uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
4291dd7eddSVarun Wadekar {
4391dd7eddSVarun Wadekar uint32_t ret = 0U;
4491dd7eddSVarun Wadekar
4591dd7eddSVarun Wadekar #if defined(TEGRA_SMMU0_BASE)
4691dd7eddSVarun Wadekar if (smmu_id == TEGRA_SMMU0) {
4791dd7eddSVarun Wadekar ret = mmio_read_32(TEGRA_SMMU0_BASE + (uint64_t)off);
4891dd7eddSVarun Wadekar }
4991dd7eddSVarun Wadekar #endif
5091dd7eddSVarun Wadekar
5191dd7eddSVarun Wadekar #if defined(TEGRA_SMMU1_BASE)
5291dd7eddSVarun Wadekar if (smmu_id == TEGRA_SMMU1) {
5391dd7eddSVarun Wadekar ret = mmio_read_32(TEGRA_SMMU1_BASE + (uint64_t)off);
5491dd7eddSVarun Wadekar }
5591dd7eddSVarun Wadekar #endif
5691dd7eddSVarun Wadekar
5791dd7eddSVarun Wadekar #if defined(TEGRA_SMMU2_BASE)
5891dd7eddSVarun Wadekar if (smmu_id == TEGRA_SMMU2) {
5991dd7eddSVarun Wadekar ret = mmio_read_32(TEGRA_SMMU2_BASE + (uint64_t)off);
6091dd7eddSVarun Wadekar }
6191dd7eddSVarun Wadekar #endif
6291dd7eddSVarun Wadekar
6391dd7eddSVarun Wadekar return ret;
6491dd7eddSVarun Wadekar }
6591dd7eddSVarun Wadekar
tegra_smmu_write_32(uint32_t smmu_id,uint32_t off,uint32_t val)6691dd7eddSVarun Wadekar static inline void tegra_smmu_write_32(uint32_t smmu_id,
6791dd7eddSVarun Wadekar uint32_t off, uint32_t val)
6891dd7eddSVarun Wadekar {
6991dd7eddSVarun Wadekar #if defined(TEGRA_SMMU0_BASE)
7091dd7eddSVarun Wadekar if (smmu_id == TEGRA_SMMU0) {
7191dd7eddSVarun Wadekar mmio_write_32(TEGRA_SMMU0_BASE + (uint64_t)off, val);
7291dd7eddSVarun Wadekar }
7391dd7eddSVarun Wadekar #endif
7491dd7eddSVarun Wadekar
7591dd7eddSVarun Wadekar #if defined(TEGRA_SMMU1_BASE)
7691dd7eddSVarun Wadekar if (smmu_id == TEGRA_SMMU1) {
7791dd7eddSVarun Wadekar mmio_write_32(TEGRA_SMMU1_BASE + (uint64_t)off, val);
7891dd7eddSVarun Wadekar }
7991dd7eddSVarun Wadekar #endif
8091dd7eddSVarun Wadekar
8191dd7eddSVarun Wadekar #if defined(TEGRA_SMMU2_BASE)
8291dd7eddSVarun Wadekar if (smmu_id == TEGRA_SMMU2) {
8391dd7eddSVarun Wadekar mmio_write_32(TEGRA_SMMU2_BASE + (uint64_t)off, val);
8491dd7eddSVarun Wadekar }
8591dd7eddSVarun Wadekar #endif
8691dd7eddSVarun Wadekar }
8791dd7eddSVarun Wadekar
884122151fSVarun Wadekar void tegra_smmu_init(void);
89*21ec61a9SVarun Wadekar void tegra_smmu_verify(void);
90bc5a86f7SSteven Kao uint32_t plat_get_num_smmu_devices(void);
914122151fSVarun Wadekar
92c3cf06f1SAntonio Nino Diaz #endif /* SMMU_H */
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