1*ce3c97c9SMarvin Hsu /* 2*ce3c97c9SMarvin Hsu * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*ce3c97c9SMarvin Hsu * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. 4*ce3c97c9SMarvin Hsu * 5*ce3c97c9SMarvin Hsu * SPDX-License-Identifier: BSD-3-Clause 6*ce3c97c9SMarvin Hsu */ 7*ce3c97c9SMarvin Hsu 8*ce3c97c9SMarvin Hsu #ifndef SECURITY_ENGINE_H 9*ce3c97c9SMarvin Hsu #define SECURITY_ENGINE_H 10*ce3c97c9SMarvin Hsu 11*ce3c97c9SMarvin Hsu /******************************************************************************* 12*ce3c97c9SMarvin Hsu * Structure definition 13*ce3c97c9SMarvin Hsu ******************************************************************************/ 14*ce3c97c9SMarvin Hsu 15*ce3c97c9SMarvin Hsu /* Security Engine Linked List */ 16*ce3c97c9SMarvin Hsu struct tegra_se_ll { 17*ce3c97c9SMarvin Hsu /* DMA buffer address */ 18*ce3c97c9SMarvin Hsu uint32_t addr; 19*ce3c97c9SMarvin Hsu /* Data length in DMA buffer */ 20*ce3c97c9SMarvin Hsu uint32_t data_len; 21*ce3c97c9SMarvin Hsu }; 22*ce3c97c9SMarvin Hsu 23*ce3c97c9SMarvin Hsu #define SE_LL_MAX_BUFFER_NUM 4 24*ce3c97c9SMarvin Hsu typedef struct tegra_se_io_lst { 25*ce3c97c9SMarvin Hsu volatile uint32_t last_buff_num; 26*ce3c97c9SMarvin Hsu volatile struct tegra_se_ll buffer[SE_LL_MAX_BUFFER_NUM]; 27*ce3c97c9SMarvin Hsu } tegra_se_io_lst_t __attribute__((aligned(4))); 28*ce3c97c9SMarvin Hsu 29*ce3c97c9SMarvin Hsu /* SE device structure */ 30*ce3c97c9SMarvin Hsu typedef struct tegra_se_dev { 31*ce3c97c9SMarvin Hsu /* Security Engine ID */ 32*ce3c97c9SMarvin Hsu const int se_num; 33*ce3c97c9SMarvin Hsu /* SE base address */ 34*ce3c97c9SMarvin Hsu const uint64_t se_base; 35*ce3c97c9SMarvin Hsu /* SE context size in AES blocks */ 36*ce3c97c9SMarvin Hsu const uint32_t ctx_size_blks; 37*ce3c97c9SMarvin Hsu /* pointer to source linked list buffer */ 38*ce3c97c9SMarvin Hsu tegra_se_io_lst_t *src_ll_buf; 39*ce3c97c9SMarvin Hsu /* pointer to destination linked list buffer */ 40*ce3c97c9SMarvin Hsu tegra_se_io_lst_t *dst_ll_buf; 41*ce3c97c9SMarvin Hsu } tegra_se_dev_t; 42*ce3c97c9SMarvin Hsu 43*ce3c97c9SMarvin Hsu /******************************************************************************* 44*ce3c97c9SMarvin Hsu * Public interface 45*ce3c97c9SMarvin Hsu ******************************************************************************/ 46*ce3c97c9SMarvin Hsu void tegra_se_init(void); 47*ce3c97c9SMarvin Hsu int tegra_se_suspend(void); 48*ce3c97c9SMarvin Hsu void tegra_se_resume(void); 49*ce3c97c9SMarvin Hsu int tegra_se_save_tzram(void); 50*ce3c97c9SMarvin Hsu 51*ce3c97c9SMarvin Hsu #endif /* SECURITY_ENGINE_H */ 52