1f1f72019SOlivier Deprez /* 2f1f72019SOlivier Deprez * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3*4eed9c84SJeetesh Burman * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. 4ce3c97c9SMarvin Hsu * 5ce3c97c9SMarvin Hsu * SPDX-License-Identifier: BSD-3-Clause 6ce3c97c9SMarvin Hsu */ 7ce3c97c9SMarvin Hsu 8ce3c97c9SMarvin Hsu #ifndef SECURITY_ENGINE_H 9ce3c97c9SMarvin Hsu #define SECURITY_ENGINE_H 10ce3c97c9SMarvin Hsu 11ce3c97c9SMarvin Hsu /******************************************************************************* 12ce3c97c9SMarvin Hsu * Structure definition 13ce3c97c9SMarvin Hsu ******************************************************************************/ 14ce3c97c9SMarvin Hsu 15ce3c97c9SMarvin Hsu /* Security Engine Linked List */ 16ce3c97c9SMarvin Hsu struct tegra_se_ll { 17ce3c97c9SMarvin Hsu /* DMA buffer address */ 18ce3c97c9SMarvin Hsu uint32_t addr; 19ce3c97c9SMarvin Hsu /* Data length in DMA buffer */ 20ce3c97c9SMarvin Hsu uint32_t data_len; 21ce3c97c9SMarvin Hsu }; 22ce3c97c9SMarvin Hsu 23ce3c97c9SMarvin Hsu #define SE_LL_MAX_BUFFER_NUM 4 24ce3c97c9SMarvin Hsu typedef struct tegra_se_io_lst { 25ce3c97c9SMarvin Hsu volatile uint32_t last_buff_num; 26ce3c97c9SMarvin Hsu volatile struct tegra_se_ll buffer[SE_LL_MAX_BUFFER_NUM]; 27ce3c97c9SMarvin Hsu } tegra_se_io_lst_t __attribute__((aligned(4))); 28ce3c97c9SMarvin Hsu 29ce3c97c9SMarvin Hsu /* SE device structure */ 30ce3c97c9SMarvin Hsu typedef struct tegra_se_dev { 31ce3c97c9SMarvin Hsu /* Security Engine ID */ 32ce3c97c9SMarvin Hsu const int se_num; 33ce3c97c9SMarvin Hsu /* SE base address */ 34ce3c97c9SMarvin Hsu const uint64_t se_base; 35ce3c97c9SMarvin Hsu /* SE context size in AES blocks */ 36ce3c97c9SMarvin Hsu const uint32_t ctx_size_blks; 37ce3c97c9SMarvin Hsu /* pointer to source linked list buffer */ 38ce3c97c9SMarvin Hsu tegra_se_io_lst_t *src_ll_buf; 39ce3c97c9SMarvin Hsu /* pointer to destination linked list buffer */ 40ce3c97c9SMarvin Hsu tegra_se_io_lst_t *dst_ll_buf; 415ed1755aSMarvin Hsu /* LP context buffer pointer */ 425ed1755aSMarvin Hsu uint32_t *ctx_save_buf; 43ce3c97c9SMarvin Hsu } tegra_se_dev_t; 44ce3c97c9SMarvin Hsu 455ed1755aSMarvin Hsu /* PKA1 device structure */ 465ed1755aSMarvin Hsu typedef struct tegra_pka_dev { 475ed1755aSMarvin Hsu /* PKA1 base address */ 485ed1755aSMarvin Hsu uint64_t pka_base; 495ed1755aSMarvin Hsu } tegra_pka_dev_t; 505ed1755aSMarvin Hsu 51ce3c97c9SMarvin Hsu /******************************************************************************* 52ce3c97c9SMarvin Hsu * Public interface 53ce3c97c9SMarvin Hsu ******************************************************************************/ 54ce3c97c9SMarvin Hsu void tegra_se_init(void); 55ce3c97c9SMarvin Hsu int tegra_se_suspend(void); 56ce3c97c9SMarvin Hsu void tegra_se_resume(void); 57ce3c97c9SMarvin Hsu int tegra_se_save_tzram(void); 58*4eed9c84SJeetesh Burman int32_t tegra_se_save_sha256_hash(uint64_t bl31_base, uint32_t src_len_inbyte); 59ce3c97c9SMarvin Hsu 60ce3c97c9SMarvin Hsu #endif /* SECURITY_ENGINE_H */ 61