xref: /rk3399_ARM-atf/plat/nvidia/tegra/include/drivers/pmc.h (revision c948f77136c42a92d0bb660543a3600c36dcf7f1)
1 /*
2  * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PMC_H
8 #define PMC_H
9 
10 #include <lib/mmio.h>
11 #include <lib/utils_def.h>
12 
13 #include <tegra_def.h>
14 
15 #define PMC_CONFIG				U(0x0)
16 #define PMC_PWRGATE_STATUS			U(0x38)
17 #define PMC_PWRGATE_TOGGLE			U(0x30)
18 #define  PMC_TOGGLE_START			U(0x100)
19 #define PMC_SCRATCH39				U(0x138)
20 #define PMC_SECURE_DISABLE2			U(0x2c4)
21 #define  PMC_SECURE_DISABLE2_WRITE22_ON		(U(1) << 28)
22 #define PMC_SECURE_SCRATCH22			U(0x338)
23 #define PMC_SECURE_DISABLE3			U(0x2d8)
24 #define  PMC_SECURE_DISABLE3_WRITE34_ON		(U(1) << 20)
25 #define  PMC_SECURE_DISABLE3_WRITE35_ON		(U(1) << 22)
26 #define PMC_SECURE_SCRATCH34			U(0x368)
27 #define PMC_SECURE_SCRATCH35			U(0x36c)
28 
29 static inline uint32_t tegra_pmc_read_32(uint32_t off)
30 {
31 	return mmio_read_32(TEGRA_PMC_BASE + off);
32 }
33 
34 static inline void tegra_pmc_write_32(uint32_t off, uint32_t val)
35 {
36 	mmio_write_32(TEGRA_PMC_BASE + off, val);
37 }
38 
39 void tegra_pmc_cpu_setup(uint64_t reset_addr);
40 void tegra_pmc_lock_cpu_vectors(void);
41 void tegra_pmc_cpu_on(int32_t cpu);
42 __dead2 void tegra_pmc_system_reset(void);
43 
44 #endif /* PMC_H */
45