1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PMC_H__ 32 #define __PMC_H__ 33 34 #include <mmio.h> 35 #include <tegra_def.h> 36 37 #define PMC_CONFIG 0x0 38 #define PMC_PWRGATE_STATUS 0x38 39 #define PMC_PWRGATE_TOGGLE 0x30 40 #define PMC_TOGGLE_START 0x100 41 #define PMC_SCRATCH39 0x138 42 #define PMC_SECURE_DISABLE2 0x2c4 43 #define PMC_SECURE_DISABLE2_WRITE22_ON (1 << 28) 44 #define PMC_SECURE_SCRATCH22 0x338 45 #define PMC_SECURE_DISABLE3 0x2d8 46 #define PMC_SECURE_DISABLE3_WRITE34_ON (1 << 20) 47 #define PMC_SECURE_DISABLE3_WRITE35_ON (1 << 22) 48 #define PMC_SECURE_SCRATCH34 0x368 49 #define PMC_SECURE_SCRATCH35 0x36c 50 51 static inline uint32_t tegra_pmc_read_32(uint32_t off) 52 { 53 return mmio_read_32(TEGRA_PMC_BASE + off); 54 } 55 56 static inline void tegra_pmc_write_32(uint32_t off, uint32_t val) 57 { 58 mmio_write_32(TEGRA_PMC_BASE + off, val); 59 } 60 61 void tegra_pmc_cpu_setup(uint64_t reset_addr); 62 void tegra_pmc_lock_cpu_vectors(void); 63 void tegra_pmc_cpu_on(int cpu); 64 __dead2 void tegra_pmc_system_reset(void); 65 66 #endif /* __PMC_H__ */ 67