xref: /rk3399_ARM-atf/plat/nvidia/tegra/include/drivers/pmc.h (revision fdc08e2ecbc18ca70001ccf1fe064a3625d36b5b)
108438e24SVarun Wadekar /*
2a7a63e0eSVarun Wadekar  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
308438e24SVarun Wadekar  *
482cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
508438e24SVarun Wadekar  */
608438e24SVarun Wadekar 
7c3cf06f1SAntonio Nino Diaz #ifndef PMC_H
8c3cf06f1SAntonio Nino Diaz #define PMC_H
908438e24SVarun Wadekar 
1009d40e0eSAntonio Nino Diaz #include <lib/mmio.h>
1109d40e0eSAntonio Nino Diaz #include <lib/utils_def.h>
12a7a63e0eSVarun Wadekar #include <stdbool.h>
1309d40e0eSAntonio Nino Diaz 
1408438e24SVarun Wadekar #include <tegra_def.h>
1508438e24SVarun Wadekar 
1631d97dc2SAnthony Zhou #define PMC_CONFIG				U(0x0)
17*fdc08e2eSkalyani chidambaram #define PMC_DPD_ENABLE_0			U(0x24)
1831d97dc2SAnthony Zhou #define PMC_PWRGATE_STATUS			U(0x38)
1931d97dc2SAnthony Zhou #define PMC_PWRGATE_TOGGLE			U(0x30)
20*fdc08e2eSkalyani chidambaram #define PMC_SECURE_SCRATCH0			U(0xb0)
21*fdc08e2eSkalyani chidambaram #define PMC_SECURE_SCRATCH5			U(0xc4)
22*fdc08e2eSkalyani chidambaram #define PMC_CRYPTO_OP_0				U(0xf4)
2331d97dc2SAnthony Zhou #define  PMC_TOGGLE_START			U(0x100)
2431d97dc2SAnthony Zhou #define PMC_SCRATCH39				U(0x138)
25*fdc08e2eSkalyani chidambaram #define PMC_SECURE_SCRATCH6			U(0x224)
26*fdc08e2eSkalyani chidambaram #define PMC_SECURE_SCRATCH7			U(0x228)
2731d97dc2SAnthony Zhou #define PMC_SECURE_DISABLE2			U(0x2c4)
2831d97dc2SAnthony Zhou #define  PMC_SECURE_DISABLE2_WRITE22_ON		(U(1) << 28)
29*fdc08e2eSkalyani chidambaram #define PMC_SECURE_SCRATCH8			U(0x300)
30*fdc08e2eSkalyani chidambaram #define PMC_SECURE_SCRATCH79			U(0x41c)
31*fdc08e2eSkalyani chidambaram #define PMC_FUSE_CONTROL_0			U(0x450)
3231d97dc2SAnthony Zhou #define PMC_SECURE_SCRATCH22			U(0x338)
3331d97dc2SAnthony Zhou #define PMC_SECURE_DISABLE3			U(0x2d8)
3431d97dc2SAnthony Zhou #define  PMC_SECURE_DISABLE3_WRITE34_ON		(U(1) << 20)
3531d97dc2SAnthony Zhou #define  PMC_SECURE_DISABLE3_WRITE35_ON		(U(1) << 22)
3631d97dc2SAnthony Zhou #define PMC_SECURE_SCRATCH34			U(0x368)
3731d97dc2SAnthony Zhou #define PMC_SECURE_SCRATCH35			U(0x36c)
38*fdc08e2eSkalyani chidambaram #define PMC_SECURE_SCRATCH80			U(0xa98)
39*fdc08e2eSkalyani chidambaram #define PMC_SECURE_SCRATCH119			U(0xb34)
403ca3c27cSVarun Wadekar #define PMC_SCRATCH201				U(0x844)
4108438e24SVarun Wadekar 
4208438e24SVarun Wadekar static inline uint32_t tegra_pmc_read_32(uint32_t off)
4308438e24SVarun Wadekar {
4408438e24SVarun Wadekar 	return mmio_read_32(TEGRA_PMC_BASE + off);
4508438e24SVarun Wadekar }
4608438e24SVarun Wadekar 
4708438e24SVarun Wadekar static inline void tegra_pmc_write_32(uint32_t off, uint32_t val)
4808438e24SVarun Wadekar {
4908438e24SVarun Wadekar 	mmio_write_32(TEGRA_PMC_BASE + off, val);
5008438e24SVarun Wadekar }
5108438e24SVarun Wadekar 
5231d97dc2SAnthony Zhou void tegra_pmc_cpu_on(int32_t cpu);
53a7a63e0eSVarun Wadekar void tegra_pmc_cpu_setup(uint64_t reset_addr);
54a7a63e0eSVarun Wadekar bool tegra_pmc_is_last_on_cpu(void);
55a7a63e0eSVarun Wadekar void tegra_pmc_lock_cpu_vectors(void);
5608438e24SVarun Wadekar __dead2 void tegra_pmc_system_reset(void);
5708438e24SVarun Wadekar 
58c3cf06f1SAntonio Nino Diaz #endif /* PMC_H */
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