108438e24SVarun Wadekar /* 2a7a63e0eSVarun Wadekar * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*24902faeSkalyani chidambaram * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 408438e24SVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 608438e24SVarun Wadekar */ 708438e24SVarun Wadekar 8c3cf06f1SAntonio Nino Diaz #ifndef PMC_H 9c3cf06f1SAntonio Nino Diaz #define PMC_H 1008438e24SVarun Wadekar 1109d40e0eSAntonio Nino Diaz #include <lib/mmio.h> 1209d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 13a7a63e0eSVarun Wadekar #include <stdbool.h> 1409d40e0eSAntonio Nino Diaz 1508438e24SVarun Wadekar #include <tegra_def.h> 1608438e24SVarun Wadekar 1731d97dc2SAnthony Zhou #define PMC_CONFIG U(0x0) 18da0f4743Skalyani chidambaram #define PMC_IO_DPD_SAMPLE U(0x20) 19fdc08e2eSkalyani chidambaram #define PMC_DPD_ENABLE_0 U(0x24) 2031d97dc2SAnthony Zhou #define PMC_PWRGATE_STATUS U(0x38) 2131d97dc2SAnthony Zhou #define PMC_PWRGATE_TOGGLE U(0x30) 22*24902faeSkalyani chidambaram #define PMC_SCRATCH1 U(0x54) 23fdc08e2eSkalyani chidambaram #define PMC_CRYPTO_OP_0 U(0xf4) 2431d97dc2SAnthony Zhou #define PMC_TOGGLE_START U(0x100) 25*24902faeSkalyani chidambaram #define PMC_SCRATCH31 U(0x118) 26*24902faeSkalyani chidambaram #define PMC_SCRATCH32 U(0x11C) 27*24902faeSkalyani chidambaram #define PMC_SCRATCH33 U(0x120) 2831d97dc2SAnthony Zhou #define PMC_SCRATCH39 U(0x138) 29*24902faeSkalyani chidambaram #define PMC_SCRATCH40 U(0x13C) 30da0f4743Skalyani chidambaram #define PMC_SCRATCH41 U(0x140) 31*24902faeSkalyani chidambaram #define PMC_SCRATCH42 U(0x144) 32*24902faeSkalyani chidambaram #define PMC_SCRATCH43 U(0x22C) 33*24902faeSkalyani chidambaram #define PMC_SCRATCH44 U(0x230) 34*24902faeSkalyani chidambaram #define PMC_SCRATCH45 U(0x234) 35*24902faeSkalyani chidambaram #define PMC_SCRATCH46 U(0x238) 36*24902faeSkalyani chidambaram #define PMC_SCRATCH47 U(0x23C) 37*24902faeSkalyani chidambaram #define PMC_SCRATCH48 U(0x240) 38*24902faeSkalyani chidambaram #define PMC_SCRATCH50 U(0x248) 39*24902faeSkalyani chidambaram #define PMC_SCRATCH51 U(0x24C) 40*24902faeSkalyani chidambaram #define PMC_TSC_MULT_0 U(0x2B4) 41*24902faeSkalyani chidambaram #define PMC_STICKY_BIT U(0x2C0) 42*24902faeSkalyani chidambaram #define PMC_SECURE_DISABLE2 U(0x2C4) 4331d97dc2SAnthony Zhou #define PMC_SECURE_DISABLE2_WRITE22_ON (U(1) << 28) 44fdc08e2eSkalyani chidambaram #define PMC_FUSE_CONTROL_0 U(0x450) 45*24902faeSkalyani chidambaram #define PMC_SECURE_DISABLE3 U(0x2D8) 4631d97dc2SAnthony Zhou #define PMC_SECURE_DISABLE3_WRITE34_ON (U(1) << 20) 4731d97dc2SAnthony Zhou #define PMC_SECURE_DISABLE3_WRITE35_ON (U(1) << 22) 48*24902faeSkalyani chidambaram #define PMC_SECURE_SCRATCH22 U(0x338) 4931d97dc2SAnthony Zhou #define PMC_SECURE_SCRATCH34 U(0x368) 5031d97dc2SAnthony Zhou #define PMC_SECURE_SCRATCH35 U(0x36c) 51*24902faeSkalyani chidambaram #define PMC_SCRATCH56 U(0x600) 52*24902faeSkalyani chidambaram #define PMC_SCRATCH57 U(0x604) 533ca3c27cSVarun Wadekar #define PMC_SCRATCH201 U(0x844) 5408438e24SVarun Wadekar tegra_pmc_read_32(uint32_t off)5508438e24SVarun Wadekarstatic inline uint32_t tegra_pmc_read_32(uint32_t off) 5608438e24SVarun Wadekar { 5708438e24SVarun Wadekar return mmio_read_32(TEGRA_PMC_BASE + off); 5808438e24SVarun Wadekar } 5908438e24SVarun Wadekar tegra_pmc_write_32(uint32_t off,uint32_t val)6008438e24SVarun Wadekarstatic inline void tegra_pmc_write_32(uint32_t off, uint32_t val) 6108438e24SVarun Wadekar { 6208438e24SVarun Wadekar mmio_write_32(TEGRA_PMC_BASE + off, val); 6308438e24SVarun Wadekar } 6408438e24SVarun Wadekar 6531d97dc2SAnthony Zhou void tegra_pmc_cpu_on(int32_t cpu); 66a7a63e0eSVarun Wadekar void tegra_pmc_cpu_setup(uint64_t reset_addr); 67a7a63e0eSVarun Wadekar bool tegra_pmc_is_last_on_cpu(void); 68a7a63e0eSVarun Wadekar void tegra_pmc_lock_cpu_vectors(void); 69da0f4743Skalyani chidambaram void tegra_pmc_resume(void); 7008438e24SVarun Wadekar __dead2 void tegra_pmc_system_reset(void); 7108438e24SVarun Wadekar 72c3cf06f1SAntonio Nino Diaz #endif /* PMC_H */ 73