121f1fd95SVarun Wadekar /* 2*50e91633SAnthony Zhou * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 321f1fd95SVarun Wadekar * 421f1fd95SVarun Wadekar * Redistribution and use in source and binary forms, with or without 521f1fd95SVarun Wadekar * modification, are permitted provided that the following conditions are met: 621f1fd95SVarun Wadekar * 721f1fd95SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 821f1fd95SVarun Wadekar * list of conditions and the following disclaimer. 921f1fd95SVarun Wadekar * 1021f1fd95SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 1121f1fd95SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 1221f1fd95SVarun Wadekar * and/or other materials provided with the distribution. 1321f1fd95SVarun Wadekar * 1421f1fd95SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 1521f1fd95SVarun Wadekar * to endorse or promote products derived from this software without specific 1621f1fd95SVarun Wadekar * prior written permission. 1721f1fd95SVarun Wadekar * 1821f1fd95SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1921f1fd95SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2021f1fd95SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2121f1fd95SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2221f1fd95SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2321f1fd95SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2421f1fd95SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2521f1fd95SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2621f1fd95SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2721f1fd95SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2821f1fd95SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 2921f1fd95SVarun Wadekar */ 3021f1fd95SVarun Wadekar 3121f1fd95SVarun Wadekar #ifndef __MEMCTRLV1_H__ 3221f1fd95SVarun Wadekar #define __MEMCTRLV1_H__ 3321f1fd95SVarun Wadekar 3421f1fd95SVarun Wadekar #include <mmio.h> 3521f1fd95SVarun Wadekar #include <tegra_def.h> 3621f1fd95SVarun Wadekar 3721f1fd95SVarun Wadekar /* SMMU registers */ 38*50e91633SAnthony Zhou #define MC_SMMU_CONFIG_0 0x10U 39*50e91633SAnthony Zhou #define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0U 40*50e91633SAnthony Zhou #define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1U 41*50e91633SAnthony Zhou #define MC_SMMU_TLB_CONFIG_0 0x14U 42*50e91633SAnthony Zhou #define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010U 43*50e91633SAnthony Zhou #define MC_SMMU_PTC_CONFIG_0 0x18U 44*50e91633SAnthony Zhou #define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003fU 45*50e91633SAnthony Zhou #define MC_SMMU_TLB_FLUSH_0 0x30U 46*50e91633SAnthony Zhou #define TLB_FLUSH_VA_MATCH_ALL 0U 47*50e91633SAnthony Zhou #define TLB_FLUSH_ASID_MATCH_DISABLE 0U 48*50e91633SAnthony Zhou #define TLB_FLUSH_ASID_MATCH_SHIFT 31U 4921f1fd95SVarun Wadekar #define MC_SMMU_TLB_FLUSH_ALL \ 5021f1fd95SVarun Wadekar (TLB_FLUSH_VA_MATCH_ALL | \ 5121f1fd95SVarun Wadekar (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) 52*50e91633SAnthony Zhou #define MC_SMMU_PTC_FLUSH_0 0x34U 53*50e91633SAnthony Zhou #define MC_SMMU_PTC_FLUSH_ALL 0U 54*50e91633SAnthony Zhou #define MC_SMMU_ASID_SECURITY_0 0x38U 55*50e91633SAnthony Zhou #define MC_SMMU_ASID_SECURITY 0U 56*50e91633SAnthony Zhou #define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228U 57*50e91633SAnthony Zhou #define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22cU 58*50e91633SAnthony Zhou #define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230U 59*50e91633SAnthony Zhou #define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234U 60*50e91633SAnthony Zhou #define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98U 6121f1fd95SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE (~0) 6221f1fd95SVarun Wadekar 630c2276e3SVarun Wadekar /* MC IRAM aperture registers */ 640c2276e3SVarun Wadekar #define MC_IRAM_BASE_LO 0x65CU 650c2276e3SVarun Wadekar #define MC_IRAM_TOP_LO 0x660U 660c2276e3SVarun Wadekar #define MC_IRAM_BASE_TOP_HI 0x980U 670c2276e3SVarun Wadekar #define MC_IRAM_REG_CTRL 0x964U 680c2276e3SVarun Wadekar #define MC_DISABLE_IRAM_CFG_WRITES 1U 690c2276e3SVarun Wadekar 7021f1fd95SVarun Wadekar static inline uint32_t tegra_mc_read_32(uint32_t off) 7121f1fd95SVarun Wadekar { 7221f1fd95SVarun Wadekar return mmio_read_32(TEGRA_MC_BASE + off); 7321f1fd95SVarun Wadekar } 7421f1fd95SVarun Wadekar 7521f1fd95SVarun Wadekar static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 7621f1fd95SVarun Wadekar { 7721f1fd95SVarun Wadekar mmio_write_32(TEGRA_MC_BASE + off, val); 7821f1fd95SVarun Wadekar } 7921f1fd95SVarun Wadekar 8021f1fd95SVarun Wadekar #endif /* __MEMCTRLV1_H__ */ 81