1*21f1fd95SVarun Wadekar /* 2*21f1fd95SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*21f1fd95SVarun Wadekar * 4*21f1fd95SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*21f1fd95SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*21f1fd95SVarun Wadekar * 7*21f1fd95SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*21f1fd95SVarun Wadekar * list of conditions and the following disclaimer. 9*21f1fd95SVarun Wadekar * 10*21f1fd95SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*21f1fd95SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*21f1fd95SVarun Wadekar * and/or other materials provided with the distribution. 13*21f1fd95SVarun Wadekar * 14*21f1fd95SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*21f1fd95SVarun Wadekar * to endorse or promote products derived from this software without specific 16*21f1fd95SVarun Wadekar * prior written permission. 17*21f1fd95SVarun Wadekar * 18*21f1fd95SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*21f1fd95SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*21f1fd95SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*21f1fd95SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*21f1fd95SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*21f1fd95SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*21f1fd95SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*21f1fd95SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*21f1fd95SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*21f1fd95SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*21f1fd95SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*21f1fd95SVarun Wadekar */ 30*21f1fd95SVarun Wadekar 31*21f1fd95SVarun Wadekar #ifndef __MEMCTRLV1_H__ 32*21f1fd95SVarun Wadekar #define __MEMCTRLV1_H__ 33*21f1fd95SVarun Wadekar 34*21f1fd95SVarun Wadekar #include <mmio.h> 35*21f1fd95SVarun Wadekar #include <tegra_def.h> 36*21f1fd95SVarun Wadekar 37*21f1fd95SVarun Wadekar /* SMMU registers */ 38*21f1fd95SVarun Wadekar #define MC_SMMU_CONFIG_0 0x10 39*21f1fd95SVarun Wadekar #define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0 40*21f1fd95SVarun Wadekar #define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1 41*21f1fd95SVarun Wadekar #define MC_SMMU_TLB_CONFIG_0 0x14 42*21f1fd95SVarun Wadekar #define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010 43*21f1fd95SVarun Wadekar #define MC_SMMU_PTC_CONFIG_0 0x18 44*21f1fd95SVarun Wadekar #define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f 45*21f1fd95SVarun Wadekar #define MC_SMMU_TLB_FLUSH_0 0x30 46*21f1fd95SVarun Wadekar #define TLB_FLUSH_VA_MATCH_ALL 0 47*21f1fd95SVarun Wadekar #define TLB_FLUSH_ASID_MATCH_DISABLE 0 48*21f1fd95SVarun Wadekar #define TLB_FLUSH_ASID_MATCH_SHIFT 31 49*21f1fd95SVarun Wadekar #define MC_SMMU_TLB_FLUSH_ALL \ 50*21f1fd95SVarun Wadekar (TLB_FLUSH_VA_MATCH_ALL | \ 51*21f1fd95SVarun Wadekar (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) 52*21f1fd95SVarun Wadekar #define MC_SMMU_PTC_FLUSH_0 0x34 53*21f1fd95SVarun Wadekar #define MC_SMMU_PTC_FLUSH_ALL 0 54*21f1fd95SVarun Wadekar #define MC_SMMU_ASID_SECURITY_0 0x38 55*21f1fd95SVarun Wadekar #define MC_SMMU_ASID_SECURITY 0 56*21f1fd95SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228 57*21f1fd95SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c 58*21f1fd95SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230 59*21f1fd95SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234 60*21f1fd95SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 61*21f1fd95SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE (~0) 62*21f1fd95SVarun Wadekar 63*21f1fd95SVarun Wadekar /* TZDRAM carveout configuration registers */ 64*21f1fd95SVarun Wadekar #define MC_SECURITY_CFG0_0 0x70 65*21f1fd95SVarun Wadekar #define MC_SECURITY_CFG1_0 0x74 66*21f1fd95SVarun Wadekar 67*21f1fd95SVarun Wadekar /* Video Memory carveout configuration registers */ 68*21f1fd95SVarun Wadekar #define MC_VIDEO_PROTECT_BASE 0x648 69*21f1fd95SVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 70*21f1fd95SVarun Wadekar 71*21f1fd95SVarun Wadekar static inline uint32_t tegra_mc_read_32(uint32_t off) 72*21f1fd95SVarun Wadekar { 73*21f1fd95SVarun Wadekar return mmio_read_32(TEGRA_MC_BASE + off); 74*21f1fd95SVarun Wadekar } 75*21f1fd95SVarun Wadekar 76*21f1fd95SVarun Wadekar static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 77*21f1fd95SVarun Wadekar { 78*21f1fd95SVarun Wadekar mmio_write_32(TEGRA_MC_BASE + off, val); 79*21f1fd95SVarun Wadekar } 80*21f1fd95SVarun Wadekar 81*21f1fd95SVarun Wadekar #endif /* __MEMCTRLV1_H__ */ 82