108438e24SVarun Wadekar /* 208438e24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 408438e24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 508438e24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 608438e24SVarun Wadekar * 708438e24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 808438e24SVarun Wadekar * list of conditions and the following disclaimer. 908438e24SVarun Wadekar * 1008438e24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 1108438e24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 1208438e24SVarun Wadekar * and/or other materials provided with the distribution. 1308438e24SVarun Wadekar * 1408438e24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 1508438e24SVarun Wadekar * to endorse or promote products derived from this software without specific 1608438e24SVarun Wadekar * prior written permission. 1708438e24SVarun Wadekar * 1808438e24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1908438e24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2008438e24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2108438e24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2208438e24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2308438e24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2408438e24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2508438e24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2608438e24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2708438e24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2808438e24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 2908438e24SVarun Wadekar */ 3008438e24SVarun Wadekar 3108438e24SVarun Wadekar #ifndef __MEMCTRL_H__ 3208438e24SVarun Wadekar #define __MEMCTRL_H__ 3308438e24SVarun Wadekar 3408438e24SVarun Wadekar #include <mmio.h> 3508438e24SVarun Wadekar #include <tegra_def.h> 3608438e24SVarun Wadekar 3708438e24SVarun Wadekar /* SMMU registers */ 3808438e24SVarun Wadekar #define MC_SMMU_CONFIG_0 0x10 3908438e24SVarun Wadekar #define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0 4008438e24SVarun Wadekar #define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1 4108438e24SVarun Wadekar #define MC_SMMU_TLB_CONFIG_0 0x14 4208438e24SVarun Wadekar #define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010 4308438e24SVarun Wadekar #define MC_SMMU_PTC_CONFIG_0 0x18 4408438e24SVarun Wadekar #define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f 4508438e24SVarun Wadekar #define MC_SMMU_TLB_FLUSH_0 0x30 4608438e24SVarun Wadekar #define TLB_FLUSH_VA_MATCH_ALL 0 4708438e24SVarun Wadekar #define TLB_FLUSH_ASID_MATCH_DISABLE 0 4808438e24SVarun Wadekar #define TLB_FLUSH_ASID_MATCH_SHIFT 31 4908438e24SVarun Wadekar #define MC_SMMU_TLB_FLUSH_ALL \ 5008438e24SVarun Wadekar (TLB_FLUSH_VA_MATCH_ALL | \ 5108438e24SVarun Wadekar (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) 5208438e24SVarun Wadekar #define MC_SMMU_PTC_FLUSH_0 0x34 5308438e24SVarun Wadekar #define MC_SMMU_PTC_FLUSH_ALL 0 5408438e24SVarun Wadekar #define MC_SMMU_ASID_SECURITY_0 0x38 5508438e24SVarun Wadekar #define MC_SMMU_ASID_SECURITY 0 5608438e24SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228 5708438e24SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c 5808438e24SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230 5908438e24SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234 6008438e24SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 6108438e24SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE (~0) 6208438e24SVarun Wadekar 6308438e24SVarun Wadekar /* TZDRAM carveout configuration registers */ 6408438e24SVarun Wadekar #define MC_SECURITY_CFG0_0 0x70 6508438e24SVarun Wadekar #define MC_SECURITY_CFG1_0 0x74 6608438e24SVarun Wadekar 67*9a964510SVarun Wadekar /* Video Memory carveout configuration registers */ 68*9a964510SVarun Wadekar #define MC_VIDEO_PROTECT_BASE 0x648 69*9a964510SVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 70*9a964510SVarun Wadekar 7108438e24SVarun Wadekar static inline uint32_t tegra_mc_read_32(uint32_t off) 7208438e24SVarun Wadekar { 7308438e24SVarun Wadekar return mmio_read_32(TEGRA_MC_BASE + off); 7408438e24SVarun Wadekar } 7508438e24SVarun Wadekar 7608438e24SVarun Wadekar static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 7708438e24SVarun Wadekar { 7808438e24SVarun Wadekar mmio_write_32(TEGRA_MC_BASE + off, val); 7908438e24SVarun Wadekar } 8008438e24SVarun Wadekar 8108438e24SVarun Wadekar void tegra_memctrl_setup(void); 8208438e24SVarun Wadekar void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes); 83*9a964510SVarun Wadekar void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes); 8408438e24SVarun Wadekar 8508438e24SVarun Wadekar #endif /* __MEMCTRL_H__ */ 86