1*08438e24SVarun Wadekar /* 2*08438e24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*08438e24SVarun Wadekar * 4*08438e24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*08438e24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*08438e24SVarun Wadekar * 7*08438e24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*08438e24SVarun Wadekar * list of conditions and the following disclaimer. 9*08438e24SVarun Wadekar * 10*08438e24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*08438e24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*08438e24SVarun Wadekar * and/or other materials provided with the distribution. 13*08438e24SVarun Wadekar * 14*08438e24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*08438e24SVarun Wadekar * to endorse or promote products derived from this software without specific 16*08438e24SVarun Wadekar * prior written permission. 17*08438e24SVarun Wadekar * 18*08438e24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*08438e24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*08438e24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*08438e24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*08438e24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*08438e24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*08438e24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*08438e24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*08438e24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*08438e24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*08438e24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*08438e24SVarun Wadekar */ 30*08438e24SVarun Wadekar 31*08438e24SVarun Wadekar #ifndef __MEMCTRL_H__ 32*08438e24SVarun Wadekar #define __MEMCTRL_H__ 33*08438e24SVarun Wadekar 34*08438e24SVarun Wadekar #include <mmio.h> 35*08438e24SVarun Wadekar #include <tegra_def.h> 36*08438e24SVarun Wadekar 37*08438e24SVarun Wadekar /* SMMU registers */ 38*08438e24SVarun Wadekar #define MC_SMMU_CONFIG_0 0x10 39*08438e24SVarun Wadekar #define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0 40*08438e24SVarun Wadekar #define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1 41*08438e24SVarun Wadekar #define MC_SMMU_TLB_CONFIG_0 0x14 42*08438e24SVarun Wadekar #define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010 43*08438e24SVarun Wadekar #define MC_SMMU_PTC_CONFIG_0 0x18 44*08438e24SVarun Wadekar #define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f 45*08438e24SVarun Wadekar #define MC_SMMU_TLB_FLUSH_0 0x30 46*08438e24SVarun Wadekar #define TLB_FLUSH_VA_MATCH_ALL 0 47*08438e24SVarun Wadekar #define TLB_FLUSH_ASID_MATCH_DISABLE 0 48*08438e24SVarun Wadekar #define TLB_FLUSH_ASID_MATCH_SHIFT 31 49*08438e24SVarun Wadekar #define MC_SMMU_TLB_FLUSH_ALL \ 50*08438e24SVarun Wadekar (TLB_FLUSH_VA_MATCH_ALL | \ 51*08438e24SVarun Wadekar (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) 52*08438e24SVarun Wadekar #define MC_SMMU_PTC_FLUSH_0 0x34 53*08438e24SVarun Wadekar #define MC_SMMU_PTC_FLUSH_ALL 0 54*08438e24SVarun Wadekar #define MC_SMMU_ASID_SECURITY_0 0x38 55*08438e24SVarun Wadekar #define MC_SMMU_ASID_SECURITY 0 56*08438e24SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228 57*08438e24SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c 58*08438e24SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230 59*08438e24SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234 60*08438e24SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 61*08438e24SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE (~0) 62*08438e24SVarun Wadekar 63*08438e24SVarun Wadekar /* TZDRAM carveout configuration registers */ 64*08438e24SVarun Wadekar #define MC_SECURITY_CFG0_0 0x70 65*08438e24SVarun Wadekar #define MC_SECURITY_CFG1_0 0x74 66*08438e24SVarun Wadekar 67*08438e24SVarun Wadekar static inline uint32_t tegra_mc_read_32(uint32_t off) 68*08438e24SVarun Wadekar { 69*08438e24SVarun Wadekar return mmio_read_32(TEGRA_MC_BASE + off); 70*08438e24SVarun Wadekar } 71*08438e24SVarun Wadekar 72*08438e24SVarun Wadekar static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 73*08438e24SVarun Wadekar { 74*08438e24SVarun Wadekar mmio_write_32(TEGRA_MC_BASE + off, val); 75*08438e24SVarun Wadekar } 76*08438e24SVarun Wadekar 77*08438e24SVarun Wadekar void tegra_memctrl_setup(void); 78*08438e24SVarun Wadekar void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes); 79*08438e24SVarun Wadekar 80*08438e24SVarun Wadekar #endif /* __MEMCTRL_H__ */ 81