xref: /rk3399_ARM-atf/plat/nvidia/tegra/include/drivers/mce.h (revision c3cf06f1a3a9b9ee8ac7a0ae505f95c45f7dca84)
106060028SVarun Wadekar /*
250e91633SAnthony Zhou  * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
306060028SVarun Wadekar  *
482cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
506060028SVarun Wadekar  */
606060028SVarun Wadekar 
7*c3cf06f1SAntonio Nino Diaz #ifndef MCE_H
8*c3cf06f1SAntonio Nino Diaz #define MCE_H
906060028SVarun Wadekar 
1006060028SVarun Wadekar #include <mmio.h>
1106060028SVarun Wadekar #include <tegra_def.h>
1206060028SVarun Wadekar 
1306060028SVarun Wadekar /*******************************************************************************
1406060028SVarun Wadekar  * MCE commands
1506060028SVarun Wadekar  ******************************************************************************/
1606060028SVarun Wadekar typedef enum mce_cmd {
1750e91633SAnthony Zhou 	MCE_CMD_ENTER_CSTATE = 0U,
1850e91633SAnthony Zhou 	MCE_CMD_UPDATE_CSTATE_INFO = 1U,
1950e91633SAnthony Zhou 	MCE_CMD_UPDATE_CROSSOVER_TIME = 2U,
2050e91633SAnthony Zhou 	MCE_CMD_READ_CSTATE_STATS = 3U,
2150e91633SAnthony Zhou 	MCE_CMD_WRITE_CSTATE_STATS = 4U,
2250e91633SAnthony Zhou 	MCE_CMD_IS_SC7_ALLOWED = 5U,
2350e91633SAnthony Zhou 	MCE_CMD_ONLINE_CORE = 6U,
2450e91633SAnthony Zhou 	MCE_CMD_CC3_CTRL = 7U,
2550e91633SAnthony Zhou 	MCE_CMD_ECHO_DATA = 8U,
2650e91633SAnthony Zhou 	MCE_CMD_READ_VERSIONS = 9U,
2750e91633SAnthony Zhou 	MCE_CMD_ENUM_FEATURES = 10U,
2850e91633SAnthony Zhou 	MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11U,
2950e91633SAnthony Zhou 	MCE_CMD_ENUM_READ_MCA = 12U,
3050e91633SAnthony Zhou 	MCE_CMD_ENUM_WRITE_MCA = 13U,
3150e91633SAnthony Zhou 	MCE_CMD_ROC_FLUSH_CACHE = 14U,
3250e91633SAnthony Zhou 	MCE_CMD_ROC_CLEAN_CACHE = 15U,
3350e91633SAnthony Zhou 	MCE_CMD_ENABLE_LATIC = 16U,
3450e91633SAnthony Zhou 	MCE_CMD_UNCORE_PERFMON_REQ = 17U,
3550e91633SAnthony Zhou 	MCE_CMD_MISC_CCPLEX = 18U,
3650e91633SAnthony Zhou 	MCE_CMD_IS_CCX_ALLOWED = 0xFEU,
3750e91633SAnthony Zhou 	MCE_CMD_MAX = 0xFFU,
3806060028SVarun Wadekar } mce_cmd_t;
3906060028SVarun Wadekar 
4050e91633SAnthony Zhou #define MCE_CMD_MASK				0xFFU
4106060028SVarun Wadekar 
4206060028SVarun Wadekar /*******************************************************************************
4306060028SVarun Wadekar  * Timeout value used to powerdown a core
4406060028SVarun Wadekar  ******************************************************************************/
4550e91633SAnthony Zhou #define MCE_CORE_SLEEP_TIME_INFINITE		0xFFFFFFFFU
4606060028SVarun Wadekar 
4706060028SVarun Wadekar /*******************************************************************************
4806060028SVarun Wadekar  * Struct to prepare UPDATE_CSTATE_INFO request
4906060028SVarun Wadekar  ******************************************************************************/
5006060028SVarun Wadekar typedef struct mce_cstate_info {
5106060028SVarun Wadekar 	/* cluster cstate value */
5206060028SVarun Wadekar 	uint32_t cluster;
5306060028SVarun Wadekar 	/* ccplex cstate value */
5406060028SVarun Wadekar 	uint32_t ccplex;
5506060028SVarun Wadekar 	/* system cstate value */
5606060028SVarun Wadekar 	uint32_t system;
5706060028SVarun Wadekar 	/* force system state? */
5806060028SVarun Wadekar 	uint8_t system_state_force;
5906060028SVarun Wadekar 	/* wake mask value */
6006060028SVarun Wadekar 	uint32_t wake_mask;
6106060028SVarun Wadekar 	/* update the wake mask? */
6206060028SVarun Wadekar 	uint8_t update_wake_mask;
6306060028SVarun Wadekar } mce_cstate_info_t;
6406060028SVarun Wadekar 
6506060028SVarun Wadekar /* public interfaces */
66ab712fd8SAnthony Zhou int mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
6706060028SVarun Wadekar 		uint64_t arg2);
6806060028SVarun Wadekar int mce_update_reset_vector(void);
6906060028SVarun Wadekar int mce_update_gsc_videomem(void);
7006060028SVarun Wadekar int mce_update_gsc_tzdram(void);
7106060028SVarun Wadekar int mce_update_gsc_tzram(void);
7206060028SVarun Wadekar __dead2 void mce_enter_ccplex_state(uint32_t state_idx);
73ab712fd8SAnthony Zhou void mce_update_cstate_info(const mce_cstate_info_t *cstate);
7406060028SVarun Wadekar void mce_verify_firmware_version(void);
7506060028SVarun Wadekar 
76*c3cf06f1SAntonio Nino Diaz #endif /* MCE_H */
77