xref: /rk3399_ARM-atf/plat/nvidia/tegra/include/drivers/bpmp.h (revision c948f77136c42a92d0bb660543a3600c36dcf7f1)
1 /*
2  * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef BPMP_H
8 #define BPMP_H
9 
10 #include <stdint.h>
11 
12 /* macro to enable clock to the Atomics block */
13 #define CAR_ENABLE_ATOMICS	(1UL << 16)
14 
15 /* command to get the channel base addresses from bpmp */
16 #define ATOMIC_CMD_GET		4UL
17 
18 /* Hardware IRQ # used to signal bpmp of an incoming command */
19 #define INT_SHR_SEM_OUTBOX_FULL	6UL
20 
21 /* macros to decode the bpmp's state */
22 #define CH_MASK(ch)		(0x3UL << ((ch) * 2UL))
23 #define MA_FREE(ch)		(0x2UL << ((ch) * 2UL))
24 #define MA_ACKD(ch)		(0x3UL << ((ch) * 2UL))
25 
26 /* response from bpmp to indicate it has powered up */
27 #define SIGN_OF_LIFE		0xAAAAAAAAUL
28 
29 /* flags to indicate bpmp driver's state */
30 #define BPMP_INIT_COMPLETE	0xBEEFF00DUL
31 #define BPMP_INIT_PENDING	0xDEADBEEFUL
32 
33 /* requests serviced by the bpmp */
34 #define MRQ_PING		0
35 #define MRQ_QUERY_TAG		1
36 #define MRQ_DO_IDLE		2
37 #define MRQ_TOLERATE_IDLE	3
38 #define MRQ_MODULE_LOAD		4
39 #define MRQ_MODULE_UNLOAD	5
40 #define MRQ_SWITCH_CLUSTER	6
41 #define MRQ_TRACE_MODIFY	7
42 #define MRQ_WRITE_TRACE		8
43 #define MRQ_THREADED_PING	9
44 #define MRQ_CPUIDLE_USAGE	10
45 #define MRQ_MODULE_MAIL		11
46 #define MRQ_SCX_ENABLE		12
47 #define MRQ_BPMPIDLE_USAGE	14
48 #define MRQ_HEAP_USAGE		15
49 #define MRQ_SCLK_SKIP_SET_RATE	16
50 #define MRQ_ENABLE_SUSPEND	17
51 #define MRQ_PASR_MASK		18
52 #define MRQ_DEBUGFS		19
53 #define MRQ_THERMAL		27
54 
55 /* Tegra PM states as known to BPMP */
56 #define TEGRA_PM_CC1		9
57 #define TEGRA_PM_CC4		12
58 #define TEGRA_PM_CC6		14
59 #define TEGRA_PM_CC7		15
60 #define TEGRA_PM_SC1		17
61 #define TEGRA_PM_SC2		18
62 #define TEGRA_PM_SC3		19
63 #define TEGRA_PM_SC4		20
64 #define TEGRA_PM_SC7		23
65 
66 /* flag to indicate if entry into a CCx power state is allowed */
67 #define BPMP_CCx_ALLOWED	0UL
68 
69 /* number of communication channels to interact with the bpmp */
70 #define NR_CHANNELS		4U
71 
72 /* flag to ask bpmp to acknowledge command packet */
73 #define NO_ACK			(0UL << 0UL)
74 #define DO_ACK			(1UL << 0UL)
75 
76 /* size of the command/response data */
77 #define MSG_DATA_MAX_SZ		120U
78 
79 /**
80  * command/response packet to/from the bpmp
81  *
82  * command
83  * -------
84  * code: MRQ_* command
85  * flags: DO_ACK or NO_ACK
86  * data:
87  * 	[0] = cpu #
88  * 	[1] = cluster power state (TEGRA_PM_CCx)
89  * 	[2] = system power state (TEGRA_PM_SCx)
90  *
91  * response
92  * ---------
93  * code: error code
94  * flags: not used
95  * data:
96  * 	[0-3] = response value
97  */
98 typedef struct mb_data {
99 	int32_t code;
100 	uint32_t flags;
101 	uint8_t data[MSG_DATA_MAX_SZ];
102 } mb_data_t;
103 
104 /**
105  * Function to initialise the interface with the bpmp
106  */
107 int tegra_bpmp_init(void);
108 
109 /**
110  * Handler to send a MRQ_* command to the bpmp
111  */
112 int32_t tegra_bpmp_send_receive_atomic(int mrq, const void *ob_data, int ob_sz,
113 		void *ib_data, int ib_sz);
114 
115 #endif /* BPMP_H */
116