1*dd1a71f1SVarun Wadekar /* 2*dd1a71f1SVarun Wadekar * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*dd1a71f1SVarun Wadekar * 4*dd1a71f1SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5*dd1a71f1SVarun Wadekar */ 6*dd1a71f1SVarun Wadekar 7*dd1a71f1SVarun Wadekar #ifndef BPMP_H 8*dd1a71f1SVarun Wadekar #define BPMP_H 9*dd1a71f1SVarun Wadekar 10*dd1a71f1SVarun Wadekar #include <stdint.h> 11*dd1a71f1SVarun Wadekar 12*dd1a71f1SVarun Wadekar /* macro to enable clock to the Atomics block */ 13*dd1a71f1SVarun Wadekar #define CAR_ENABLE_ATOMICS (1UL << 16) 14*dd1a71f1SVarun Wadekar 15*dd1a71f1SVarun Wadekar /* command to get the channel base addresses from bpmp */ 16*dd1a71f1SVarun Wadekar #define ATOMIC_CMD_GET 4UL 17*dd1a71f1SVarun Wadekar 18*dd1a71f1SVarun Wadekar /* Hardware IRQ # used to signal bpmp of an incoming command */ 19*dd1a71f1SVarun Wadekar #define INT_SHR_SEM_OUTBOX_FULL 6UL 20*dd1a71f1SVarun Wadekar 21*dd1a71f1SVarun Wadekar /* macros to decode the bpmp's state */ 22*dd1a71f1SVarun Wadekar #define CH_MASK(ch) (0x3UL << ((ch) * 2UL)) 23*dd1a71f1SVarun Wadekar #define MA_FREE(ch) (0x2UL << ((ch) * 2UL)) 24*dd1a71f1SVarun Wadekar #define MA_ACKD(ch) (0x3UL << ((ch) * 2UL)) 25*dd1a71f1SVarun Wadekar 26*dd1a71f1SVarun Wadekar /* response from bpmp to indicate it has powered up */ 27*dd1a71f1SVarun Wadekar #define SIGN_OF_LIFE 0xAAAAAAAAUL 28*dd1a71f1SVarun Wadekar 29*dd1a71f1SVarun Wadekar /* flags to indicate bpmp driver's state */ 30*dd1a71f1SVarun Wadekar #define BPMP_INIT_COMPLETE 0xBEEFF00DUL 31*dd1a71f1SVarun Wadekar #define BPMP_INIT_PENDING 0xDEADBEEFUL 32*dd1a71f1SVarun Wadekar 33*dd1a71f1SVarun Wadekar /* requests serviced by the bpmp */ 34*dd1a71f1SVarun Wadekar #define MRQ_PING 0 35*dd1a71f1SVarun Wadekar #define MRQ_QUERY_TAG 1 36*dd1a71f1SVarun Wadekar #define MRQ_DO_IDLE 2 37*dd1a71f1SVarun Wadekar #define MRQ_TOLERATE_IDLE 3 38*dd1a71f1SVarun Wadekar #define MRQ_MODULE_LOAD 4 39*dd1a71f1SVarun Wadekar #define MRQ_MODULE_UNLOAD 5 40*dd1a71f1SVarun Wadekar #define MRQ_SWITCH_CLUSTER 6 41*dd1a71f1SVarun Wadekar #define MRQ_TRACE_MODIFY 7 42*dd1a71f1SVarun Wadekar #define MRQ_WRITE_TRACE 8 43*dd1a71f1SVarun Wadekar #define MRQ_THREADED_PING 9 44*dd1a71f1SVarun Wadekar #define MRQ_CPUIDLE_USAGE 10 45*dd1a71f1SVarun Wadekar #define MRQ_MODULE_MAIL 11 46*dd1a71f1SVarun Wadekar #define MRQ_SCX_ENABLE 12 47*dd1a71f1SVarun Wadekar #define MRQ_BPMPIDLE_USAGE 14 48*dd1a71f1SVarun Wadekar #define MRQ_HEAP_USAGE 15 49*dd1a71f1SVarun Wadekar #define MRQ_SCLK_SKIP_SET_RATE 16 50*dd1a71f1SVarun Wadekar #define MRQ_ENABLE_SUSPEND 17 51*dd1a71f1SVarun Wadekar #define MRQ_PASR_MASK 18 52*dd1a71f1SVarun Wadekar #define MRQ_DEBUGFS 19 53*dd1a71f1SVarun Wadekar #define MRQ_THERMAL 27 54*dd1a71f1SVarun Wadekar 55*dd1a71f1SVarun Wadekar /* Tegra PM states as known to BPMP */ 56*dd1a71f1SVarun Wadekar #define TEGRA_PM_CC1 9 57*dd1a71f1SVarun Wadekar #define TEGRA_PM_CC4 12 58*dd1a71f1SVarun Wadekar #define TEGRA_PM_CC6 14 59*dd1a71f1SVarun Wadekar #define TEGRA_PM_CC7 15 60*dd1a71f1SVarun Wadekar #define TEGRA_PM_SC1 17 61*dd1a71f1SVarun Wadekar #define TEGRA_PM_SC2 18 62*dd1a71f1SVarun Wadekar #define TEGRA_PM_SC3 19 63*dd1a71f1SVarun Wadekar #define TEGRA_PM_SC4 20 64*dd1a71f1SVarun Wadekar #define TEGRA_PM_SC7 23 65*dd1a71f1SVarun Wadekar 66*dd1a71f1SVarun Wadekar /* flag to indicate if entry into a CCx power state is allowed */ 67*dd1a71f1SVarun Wadekar #define BPMP_CCx_ALLOWED 0UL 68*dd1a71f1SVarun Wadekar 69*dd1a71f1SVarun Wadekar /* number of communication channels to interact with the bpmp */ 70*dd1a71f1SVarun Wadekar #define NR_CHANNELS 4U 71*dd1a71f1SVarun Wadekar 72*dd1a71f1SVarun Wadekar /* flag to ask bpmp to acknowledge command packet */ 73*dd1a71f1SVarun Wadekar #define NO_ACK (0UL << 0UL) 74*dd1a71f1SVarun Wadekar #define DO_ACK (1UL << 0UL) 75*dd1a71f1SVarun Wadekar 76*dd1a71f1SVarun Wadekar /* size of the command/response data */ 77*dd1a71f1SVarun Wadekar #define MSG_DATA_MAX_SZ 120U 78*dd1a71f1SVarun Wadekar 79*dd1a71f1SVarun Wadekar /** 80*dd1a71f1SVarun Wadekar * command/response packet to/from the bpmp 81*dd1a71f1SVarun Wadekar * 82*dd1a71f1SVarun Wadekar * command 83*dd1a71f1SVarun Wadekar * ------- 84*dd1a71f1SVarun Wadekar * code: MRQ_* command 85*dd1a71f1SVarun Wadekar * flags: DO_ACK or NO_ACK 86*dd1a71f1SVarun Wadekar * data: 87*dd1a71f1SVarun Wadekar * [0] = cpu # 88*dd1a71f1SVarun Wadekar * [1] = cluster power state (TEGRA_PM_CCx) 89*dd1a71f1SVarun Wadekar * [2] = system power state (TEGRA_PM_SCx) 90*dd1a71f1SVarun Wadekar * 91*dd1a71f1SVarun Wadekar * response 92*dd1a71f1SVarun Wadekar * --------- 93*dd1a71f1SVarun Wadekar * code: error code 94*dd1a71f1SVarun Wadekar * flags: not used 95*dd1a71f1SVarun Wadekar * data: 96*dd1a71f1SVarun Wadekar * [0-3] = response value 97*dd1a71f1SVarun Wadekar */ 98*dd1a71f1SVarun Wadekar typedef struct mb_data { 99*dd1a71f1SVarun Wadekar int32_t code; 100*dd1a71f1SVarun Wadekar uint32_t flags; 101*dd1a71f1SVarun Wadekar uint8_t data[MSG_DATA_MAX_SZ]; 102*dd1a71f1SVarun Wadekar } mb_data_t; 103*dd1a71f1SVarun Wadekar 104*dd1a71f1SVarun Wadekar /** 105*dd1a71f1SVarun Wadekar * Function to initialise the interface with the bpmp 106*dd1a71f1SVarun Wadekar */ 107*dd1a71f1SVarun Wadekar int tegra_bpmp_init(void); 108*dd1a71f1SVarun Wadekar 109*dd1a71f1SVarun Wadekar /** 110*dd1a71f1SVarun Wadekar * Handler to send a MRQ_* command to the bpmp 111*dd1a71f1SVarun Wadekar */ 112*dd1a71f1SVarun Wadekar int32_t tegra_bpmp_send_receive_atomic(int mrq, const void *ob_data, int ob_sz, 113*dd1a71f1SVarun Wadekar void *ib_data, int ib_sz); 114*dd1a71f1SVarun Wadekar 115*dd1a71f1SVarun Wadekar #endif /* BPMP_H */ 116