1dd1a71f1SVarun Wadekar /* 2dd1a71f1SVarun Wadekar * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3dd1a71f1SVarun Wadekar * 4dd1a71f1SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5dd1a71f1SVarun Wadekar */ 6dd1a71f1SVarun Wadekar 7dd1a71f1SVarun Wadekar #ifndef BPMP_H 8dd1a71f1SVarun Wadekar #define BPMP_H 9dd1a71f1SVarun Wadekar 10dd1a71f1SVarun Wadekar #include <stdint.h> 11dd1a71f1SVarun Wadekar 12dd1a71f1SVarun Wadekar /* macro to enable clock to the Atomics block */ 13aa64c5fbSAnthony Zhou #define CAR_ENABLE_ATOMICS (1U << 16) 14dd1a71f1SVarun Wadekar 15dd1a71f1SVarun Wadekar /* command to get the channel base addresses from bpmp */ 16aa64c5fbSAnthony Zhou #define ATOMIC_CMD_GET 4U 17dd1a71f1SVarun Wadekar 18dd1a71f1SVarun Wadekar /* Hardware IRQ # used to signal bpmp of an incoming command */ 19aa64c5fbSAnthony Zhou #define INT_SHR_SEM_OUTBOX_FULL 6U 20dd1a71f1SVarun Wadekar 21dd1a71f1SVarun Wadekar /* macros to decode the bpmp's state */ 22aa64c5fbSAnthony Zhou #define CH_MASK(ch) ((uint32_t)0x3 << ((ch) * 2U)) 23aa64c5fbSAnthony Zhou #define MA_FREE(ch) ((uint32_t)0x2 << ((ch) * 2U)) 24aa64c5fbSAnthony Zhou #define MA_ACKD(ch) ((uint32_t)0x3 << ((ch) * 2U)) 25dd1a71f1SVarun Wadekar 26dd1a71f1SVarun Wadekar /* response from bpmp to indicate it has powered up */ 27aa64c5fbSAnthony Zhou #define SIGN_OF_LIFE 0xAAAAAAAAU 28dd1a71f1SVarun Wadekar 29dd1a71f1SVarun Wadekar /* flags to indicate bpmp driver's state */ 30aa64c5fbSAnthony Zhou #define BPMP_INIT_COMPLETE 0xBEEFF00DU 31aa64c5fbSAnthony Zhou #define BPMP_INIT_PENDING 0xDEADBEEFU 32*d37a1322SVarun Wadekar #define BPMP_SUSPEND_ENTRY 0xF00DCAFEU 33dd1a71f1SVarun Wadekar 34dd1a71f1SVarun Wadekar /* requests serviced by the bpmp */ 35dd1a71f1SVarun Wadekar #define MRQ_PING 0 36dd1a71f1SVarun Wadekar #define MRQ_QUERY_TAG 1 37dd1a71f1SVarun Wadekar #define MRQ_DO_IDLE 2 38dd1a71f1SVarun Wadekar #define MRQ_TOLERATE_IDLE 3 39dd1a71f1SVarun Wadekar #define MRQ_MODULE_LOAD 4 40dd1a71f1SVarun Wadekar #define MRQ_MODULE_UNLOAD 5 41dd1a71f1SVarun Wadekar #define MRQ_SWITCH_CLUSTER 6 42dd1a71f1SVarun Wadekar #define MRQ_TRACE_MODIFY 7 43dd1a71f1SVarun Wadekar #define MRQ_WRITE_TRACE 8 44dd1a71f1SVarun Wadekar #define MRQ_THREADED_PING 9 45dd1a71f1SVarun Wadekar #define MRQ_CPUIDLE_USAGE 10 46dd1a71f1SVarun Wadekar #define MRQ_MODULE_MAIL 11 47dd1a71f1SVarun Wadekar #define MRQ_SCX_ENABLE 12 48dd1a71f1SVarun Wadekar #define MRQ_BPMPIDLE_USAGE 14 49dd1a71f1SVarun Wadekar #define MRQ_HEAP_USAGE 15 50dd1a71f1SVarun Wadekar #define MRQ_SCLK_SKIP_SET_RATE 16 51dd1a71f1SVarun Wadekar #define MRQ_ENABLE_SUSPEND 17 52dd1a71f1SVarun Wadekar #define MRQ_PASR_MASK 18 53dd1a71f1SVarun Wadekar #define MRQ_DEBUGFS 19 54dd1a71f1SVarun Wadekar #define MRQ_THERMAL 27 55dd1a71f1SVarun Wadekar 56dd1a71f1SVarun Wadekar /* Tegra PM states as known to BPMP */ 57dd1a71f1SVarun Wadekar #define TEGRA_PM_CC1 9 58dd1a71f1SVarun Wadekar #define TEGRA_PM_CC4 12 59dd1a71f1SVarun Wadekar #define TEGRA_PM_CC6 14 60dd1a71f1SVarun Wadekar #define TEGRA_PM_CC7 15 61dd1a71f1SVarun Wadekar #define TEGRA_PM_SC1 17 62dd1a71f1SVarun Wadekar #define TEGRA_PM_SC2 18 63dd1a71f1SVarun Wadekar #define TEGRA_PM_SC3 19 64dd1a71f1SVarun Wadekar #define TEGRA_PM_SC4 20 65dd1a71f1SVarun Wadekar #define TEGRA_PM_SC7 23 66dd1a71f1SVarun Wadekar 67dd1a71f1SVarun Wadekar /* flag to indicate if entry into a CCx power state is allowed */ 68aa64c5fbSAnthony Zhou #define BPMP_CCx_ALLOWED 0U 69dd1a71f1SVarun Wadekar 70dd1a71f1SVarun Wadekar /* number of communication channels to interact with the bpmp */ 71dd1a71f1SVarun Wadekar #define NR_CHANNELS 4U 72dd1a71f1SVarun Wadekar 73dd1a71f1SVarun Wadekar /* flag to ask bpmp to acknowledge command packet */ 74aa64c5fbSAnthony Zhou #define NO_ACK (0U << 0U) 75aa64c5fbSAnthony Zhou #define DO_ACK (1U << 0U) 76dd1a71f1SVarun Wadekar 77dd1a71f1SVarun Wadekar /* size of the command/response data */ 78dd1a71f1SVarun Wadekar #define MSG_DATA_MAX_SZ 120U 79dd1a71f1SVarun Wadekar 80dd1a71f1SVarun Wadekar /** 81dd1a71f1SVarun Wadekar * command/response packet to/from the bpmp 82dd1a71f1SVarun Wadekar * 83dd1a71f1SVarun Wadekar * command 84dd1a71f1SVarun Wadekar * ------- 85dd1a71f1SVarun Wadekar * code: MRQ_* command 86dd1a71f1SVarun Wadekar * flags: DO_ACK or NO_ACK 87dd1a71f1SVarun Wadekar * data: 88dd1a71f1SVarun Wadekar * [0] = cpu # 89dd1a71f1SVarun Wadekar * [1] = cluster power state (TEGRA_PM_CCx) 90dd1a71f1SVarun Wadekar * [2] = system power state (TEGRA_PM_SCx) 91dd1a71f1SVarun Wadekar * 92dd1a71f1SVarun Wadekar * response 93dd1a71f1SVarun Wadekar * --------- 94dd1a71f1SVarun Wadekar * code: error code 95dd1a71f1SVarun Wadekar * flags: not used 96dd1a71f1SVarun Wadekar * data: 97dd1a71f1SVarun Wadekar * [0-3] = response value 98dd1a71f1SVarun Wadekar */ 99dd1a71f1SVarun Wadekar typedef struct mb_data { 100dd1a71f1SVarun Wadekar int32_t code; 101dd1a71f1SVarun Wadekar uint32_t flags; 102dd1a71f1SVarun Wadekar uint8_t data[MSG_DATA_MAX_SZ]; 103dd1a71f1SVarun Wadekar } mb_data_t; 104dd1a71f1SVarun Wadekar 105dd1a71f1SVarun Wadekar /** 106dd1a71f1SVarun Wadekar * Function to initialise the interface with the bpmp 107dd1a71f1SVarun Wadekar */ 108dd1a71f1SVarun Wadekar int tegra_bpmp_init(void); 109dd1a71f1SVarun Wadekar 110dd1a71f1SVarun Wadekar /** 111*d37a1322SVarun Wadekar * Function to suspend the interface with the bpmp 112*d37a1322SVarun Wadekar */ 113*d37a1322SVarun Wadekar void tegra_bpmp_suspend(void); 114*d37a1322SVarun Wadekar 115*d37a1322SVarun Wadekar /** 116*d37a1322SVarun Wadekar * Function to resume the interface with the bpmp 117*d37a1322SVarun Wadekar */ 118*d37a1322SVarun Wadekar void tegra_bpmp_resume(void); 119*d37a1322SVarun Wadekar 120*d37a1322SVarun Wadekar /** 121dd1a71f1SVarun Wadekar * Handler to send a MRQ_* command to the bpmp 122dd1a71f1SVarun Wadekar */ 123dd1a71f1SVarun Wadekar int32_t tegra_bpmp_send_receive_atomic(int mrq, const void *ob_data, int ob_sz, 124dd1a71f1SVarun Wadekar void *ib_data, int ib_sz); 125dd1a71f1SVarun Wadekar 126dd1a71f1SVarun Wadekar #endif /* BPMP_H */ 127