1dd1a71f1SVarun Wadekar /* 2dd1a71f1SVarun Wadekar * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3dd1a71f1SVarun Wadekar * 4dd1a71f1SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5dd1a71f1SVarun Wadekar */ 6dd1a71f1SVarun Wadekar 7dd1a71f1SVarun Wadekar #ifndef BPMP_H 8dd1a71f1SVarun Wadekar #define BPMP_H 9dd1a71f1SVarun Wadekar 10dd1a71f1SVarun Wadekar #include <stdint.h> 11dd1a71f1SVarun Wadekar 12dd1a71f1SVarun Wadekar /* macro to enable clock to the Atomics block */ 13*aa64c5fbSAnthony Zhou #define CAR_ENABLE_ATOMICS (1U << 16) 14dd1a71f1SVarun Wadekar 15dd1a71f1SVarun Wadekar /* command to get the channel base addresses from bpmp */ 16*aa64c5fbSAnthony Zhou #define ATOMIC_CMD_GET 4U 17dd1a71f1SVarun Wadekar 18dd1a71f1SVarun Wadekar /* Hardware IRQ # used to signal bpmp of an incoming command */ 19*aa64c5fbSAnthony Zhou #define INT_SHR_SEM_OUTBOX_FULL 6U 20dd1a71f1SVarun Wadekar 21dd1a71f1SVarun Wadekar /* macros to decode the bpmp's state */ 22*aa64c5fbSAnthony Zhou #define CH_MASK(ch) ((uint32_t)0x3 << ((ch) * 2U)) 23*aa64c5fbSAnthony Zhou #define MA_FREE(ch) ((uint32_t)0x2 << ((ch) * 2U)) 24*aa64c5fbSAnthony Zhou #define MA_ACKD(ch) ((uint32_t)0x3 << ((ch) * 2U)) 25dd1a71f1SVarun Wadekar 26dd1a71f1SVarun Wadekar /* response from bpmp to indicate it has powered up */ 27*aa64c5fbSAnthony Zhou #define SIGN_OF_LIFE 0xAAAAAAAAU 28dd1a71f1SVarun Wadekar 29dd1a71f1SVarun Wadekar /* flags to indicate bpmp driver's state */ 30*aa64c5fbSAnthony Zhou #define BPMP_INIT_COMPLETE 0xBEEFF00DU 31*aa64c5fbSAnthony Zhou #define BPMP_INIT_PENDING 0xDEADBEEFU 32dd1a71f1SVarun Wadekar 33dd1a71f1SVarun Wadekar /* requests serviced by the bpmp */ 34dd1a71f1SVarun Wadekar #define MRQ_PING 0 35dd1a71f1SVarun Wadekar #define MRQ_QUERY_TAG 1 36dd1a71f1SVarun Wadekar #define MRQ_DO_IDLE 2 37dd1a71f1SVarun Wadekar #define MRQ_TOLERATE_IDLE 3 38dd1a71f1SVarun Wadekar #define MRQ_MODULE_LOAD 4 39dd1a71f1SVarun Wadekar #define MRQ_MODULE_UNLOAD 5 40dd1a71f1SVarun Wadekar #define MRQ_SWITCH_CLUSTER 6 41dd1a71f1SVarun Wadekar #define MRQ_TRACE_MODIFY 7 42dd1a71f1SVarun Wadekar #define MRQ_WRITE_TRACE 8 43dd1a71f1SVarun Wadekar #define MRQ_THREADED_PING 9 44dd1a71f1SVarun Wadekar #define MRQ_CPUIDLE_USAGE 10 45dd1a71f1SVarun Wadekar #define MRQ_MODULE_MAIL 11 46dd1a71f1SVarun Wadekar #define MRQ_SCX_ENABLE 12 47dd1a71f1SVarun Wadekar #define MRQ_BPMPIDLE_USAGE 14 48dd1a71f1SVarun Wadekar #define MRQ_HEAP_USAGE 15 49dd1a71f1SVarun Wadekar #define MRQ_SCLK_SKIP_SET_RATE 16 50dd1a71f1SVarun Wadekar #define MRQ_ENABLE_SUSPEND 17 51dd1a71f1SVarun Wadekar #define MRQ_PASR_MASK 18 52dd1a71f1SVarun Wadekar #define MRQ_DEBUGFS 19 53dd1a71f1SVarun Wadekar #define MRQ_THERMAL 27 54dd1a71f1SVarun Wadekar 55dd1a71f1SVarun Wadekar /* Tegra PM states as known to BPMP */ 56dd1a71f1SVarun Wadekar #define TEGRA_PM_CC1 9 57dd1a71f1SVarun Wadekar #define TEGRA_PM_CC4 12 58dd1a71f1SVarun Wadekar #define TEGRA_PM_CC6 14 59dd1a71f1SVarun Wadekar #define TEGRA_PM_CC7 15 60dd1a71f1SVarun Wadekar #define TEGRA_PM_SC1 17 61dd1a71f1SVarun Wadekar #define TEGRA_PM_SC2 18 62dd1a71f1SVarun Wadekar #define TEGRA_PM_SC3 19 63dd1a71f1SVarun Wadekar #define TEGRA_PM_SC4 20 64dd1a71f1SVarun Wadekar #define TEGRA_PM_SC7 23 65dd1a71f1SVarun Wadekar 66dd1a71f1SVarun Wadekar /* flag to indicate if entry into a CCx power state is allowed */ 67*aa64c5fbSAnthony Zhou #define BPMP_CCx_ALLOWED 0U 68dd1a71f1SVarun Wadekar 69dd1a71f1SVarun Wadekar /* number of communication channels to interact with the bpmp */ 70dd1a71f1SVarun Wadekar #define NR_CHANNELS 4U 71dd1a71f1SVarun Wadekar 72dd1a71f1SVarun Wadekar /* flag to ask bpmp to acknowledge command packet */ 73*aa64c5fbSAnthony Zhou #define NO_ACK (0U << 0U) 74*aa64c5fbSAnthony Zhou #define DO_ACK (1U << 0U) 75dd1a71f1SVarun Wadekar 76dd1a71f1SVarun Wadekar /* size of the command/response data */ 77dd1a71f1SVarun Wadekar #define MSG_DATA_MAX_SZ 120U 78dd1a71f1SVarun Wadekar 79dd1a71f1SVarun Wadekar /** 80dd1a71f1SVarun Wadekar * command/response packet to/from the bpmp 81dd1a71f1SVarun Wadekar * 82dd1a71f1SVarun Wadekar * command 83dd1a71f1SVarun Wadekar * ------- 84dd1a71f1SVarun Wadekar * code: MRQ_* command 85dd1a71f1SVarun Wadekar * flags: DO_ACK or NO_ACK 86dd1a71f1SVarun Wadekar * data: 87dd1a71f1SVarun Wadekar * [0] = cpu # 88dd1a71f1SVarun Wadekar * [1] = cluster power state (TEGRA_PM_CCx) 89dd1a71f1SVarun Wadekar * [2] = system power state (TEGRA_PM_SCx) 90dd1a71f1SVarun Wadekar * 91dd1a71f1SVarun Wadekar * response 92dd1a71f1SVarun Wadekar * --------- 93dd1a71f1SVarun Wadekar * code: error code 94dd1a71f1SVarun Wadekar * flags: not used 95dd1a71f1SVarun Wadekar * data: 96dd1a71f1SVarun Wadekar * [0-3] = response value 97dd1a71f1SVarun Wadekar */ 98dd1a71f1SVarun Wadekar typedef struct mb_data { 99dd1a71f1SVarun Wadekar int32_t code; 100dd1a71f1SVarun Wadekar uint32_t flags; 101dd1a71f1SVarun Wadekar uint8_t data[MSG_DATA_MAX_SZ]; 102dd1a71f1SVarun Wadekar } mb_data_t; 103dd1a71f1SVarun Wadekar 104dd1a71f1SVarun Wadekar /** 105dd1a71f1SVarun Wadekar * Function to initialise the interface with the bpmp 106dd1a71f1SVarun Wadekar */ 107dd1a71f1SVarun Wadekar int tegra_bpmp_init(void); 108dd1a71f1SVarun Wadekar 109dd1a71f1SVarun Wadekar /** 110dd1a71f1SVarun Wadekar * Handler to send a MRQ_* command to the bpmp 111dd1a71f1SVarun Wadekar */ 112dd1a71f1SVarun Wadekar int32_t tegra_bpmp_send_receive_atomic(int mrq, const void *ob_data, int ob_sz, 113dd1a71f1SVarun Wadekar void *ib_data, int ib_sz); 114dd1a71f1SVarun Wadekar 115dd1a71f1SVarun Wadekar #endif /* BPMP_H */ 116