1*e2469d82SVarun Wadekar /* 2*e2469d82SVarun Wadekar * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3*e2469d82SVarun Wadekar * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4*e2469d82SVarun Wadekar * 5*e2469d82SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 6*e2469d82SVarun Wadekar */ 7*e2469d82SVarun Wadekar 8*e2469d82SVarun Wadekar #include <assert.h> 9*e2469d82SVarun Wadekar #include <string.h> 10*e2469d82SVarun Wadekar 11*e2469d82SVarun Wadekar #include <platform_def.h> 12*e2469d82SVarun Wadekar 13*e2469d82SVarun Wadekar #include <common/bl_common.h> 14*e2469d82SVarun Wadekar #include <common/debug.h> 15*e2469d82SVarun Wadekar 16*e2469d82SVarun Wadekar #include <smmu.h> 17*e2469d82SVarun Wadekar #include <tegra_private.h> 18*e2469d82SVarun Wadekar 19*e2469d82SVarun Wadekar extern void memcpy16(void *dest, const void *src, unsigned int length); 20*e2469d82SVarun Wadekar 21*e2469d82SVarun Wadekar #define SMMU_NUM_CONTEXTS 64U 22*e2469d82SVarun Wadekar #define SMMU_CONTEXT_BANK_MAX_IDX 64U 23*e2469d82SVarun Wadekar 24*e2469d82SVarun Wadekar /* 25*e2469d82SVarun Wadekar * Init SMMU during boot or "System Suspend" exit 26*e2469d82SVarun Wadekar */ 27*e2469d82SVarun Wadekar void tegra_smmu_init(void) 28*e2469d82SVarun Wadekar { 29*e2469d82SVarun Wadekar uint32_t val, cb_idx, smmu_id, ctx_base; 30*e2469d82SVarun Wadekar uint32_t smmu_counter = plat_get_num_smmu_devices(); 31*e2469d82SVarun Wadekar 32*e2469d82SVarun Wadekar for (smmu_id = 0U; smmu_id < smmu_counter; smmu_id++) { 33*e2469d82SVarun Wadekar /* Program the SMMU pagesize and reset CACHE_LOCK bit */ 34*e2469d82SVarun Wadekar val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR); 35*e2469d82SVarun Wadekar val |= SMMU_GSR0_PGSIZE_64K; 36*e2469d82SVarun Wadekar val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; 37*e2469d82SVarun Wadekar tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val); 38*e2469d82SVarun Wadekar 39*e2469d82SVarun Wadekar /* reset CACHE LOCK bit for NS Aux. Config. Register */ 40*e2469d82SVarun Wadekar val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR); 41*e2469d82SVarun Wadekar val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; 42*e2469d82SVarun Wadekar tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val); 43*e2469d82SVarun Wadekar 44*e2469d82SVarun Wadekar /* disable TCU prefetch for all contexts */ 45*e2469d82SVarun Wadekar ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) 46*e2469d82SVarun Wadekar + SMMU_CBn_ACTLR; 47*e2469d82SVarun Wadekar for (cb_idx = 0; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) { 48*e2469d82SVarun Wadekar val = tegra_smmu_read_32(smmu_id, 49*e2469d82SVarun Wadekar ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx)); 50*e2469d82SVarun Wadekar val &= (uint32_t)~SMMU_CBn_ACTLR_CPRE_BIT; 51*e2469d82SVarun Wadekar tegra_smmu_write_32(smmu_id, ctx_base + 52*e2469d82SVarun Wadekar (SMMU_GSR0_PGSIZE_64K * cb_idx), val); 53*e2469d82SVarun Wadekar } 54*e2469d82SVarun Wadekar 55*e2469d82SVarun Wadekar /* set CACHE LOCK bit for NS Aux. Config. Register */ 56*e2469d82SVarun Wadekar val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR); 57*e2469d82SVarun Wadekar val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT; 58*e2469d82SVarun Wadekar tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val); 59*e2469d82SVarun Wadekar 60*e2469d82SVarun Wadekar /* set CACHE LOCK bit for S Aux. Config. Register */ 61*e2469d82SVarun Wadekar val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR); 62*e2469d82SVarun Wadekar val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT; 63*e2469d82SVarun Wadekar tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val); 64*e2469d82SVarun Wadekar } 65*e2469d82SVarun Wadekar } 66