1e2469d82SVarun Wadekar /*
2e2469d82SVarun Wadekar * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
3e2469d82SVarun Wadekar * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4e2469d82SVarun Wadekar *
5e2469d82SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause
6e2469d82SVarun Wadekar */
7e2469d82SVarun Wadekar
8e2469d82SVarun Wadekar #include <assert.h>
9e2469d82SVarun Wadekar #include <string.h>
10e2469d82SVarun Wadekar
11e2469d82SVarun Wadekar #include <platform_def.h>
12e2469d82SVarun Wadekar
13e2469d82SVarun Wadekar #include <common/bl_common.h>
14e2469d82SVarun Wadekar #include <common/debug.h>
15e2469d82SVarun Wadekar
16e2469d82SVarun Wadekar #include <smmu.h>
17*21ec61a9SVarun Wadekar #include <tegra_platform.h>
18e2469d82SVarun Wadekar #include <tegra_private.h>
19e2469d82SVarun Wadekar
20e2469d82SVarun Wadekar extern void memcpy16(void *dest, const void *src, unsigned int length);
21e2469d82SVarun Wadekar
22e2469d82SVarun Wadekar #define SMMU_NUM_CONTEXTS 64U
23e2469d82SVarun Wadekar #define SMMU_CONTEXT_BANK_MAX_IDX 64U
24e2469d82SVarun Wadekar
25*21ec61a9SVarun Wadekar #define MISMATCH_DETECTED 0x55AA55AAU
26*21ec61a9SVarun Wadekar
27e2469d82SVarun Wadekar /*
28e2469d82SVarun Wadekar * Init SMMU during boot or "System Suspend" exit
29e2469d82SVarun Wadekar */
tegra_smmu_init(void)30e2469d82SVarun Wadekar void tegra_smmu_init(void)
31e2469d82SVarun Wadekar {
32e2469d82SVarun Wadekar uint32_t val, cb_idx, smmu_id, ctx_base;
33*21ec61a9SVarun Wadekar uint32_t num_smmu_devices = plat_get_num_smmu_devices();
34e2469d82SVarun Wadekar
35*21ec61a9SVarun Wadekar for (smmu_id = 0U; smmu_id < num_smmu_devices; smmu_id++) {
36e2469d82SVarun Wadekar /* Program the SMMU pagesize and reset CACHE_LOCK bit */
37e2469d82SVarun Wadekar val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
38e2469d82SVarun Wadekar val |= SMMU_GSR0_PGSIZE_64K;
39e2469d82SVarun Wadekar val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
40e2469d82SVarun Wadekar tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
41e2469d82SVarun Wadekar
42e2469d82SVarun Wadekar /* reset CACHE LOCK bit for NS Aux. Config. Register */
43e2469d82SVarun Wadekar val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
44e2469d82SVarun Wadekar val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
45e2469d82SVarun Wadekar tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
46e2469d82SVarun Wadekar
47e2469d82SVarun Wadekar /* disable TCU prefetch for all contexts */
48e2469d82SVarun Wadekar ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS)
49e2469d82SVarun Wadekar + SMMU_CBn_ACTLR;
50*21ec61a9SVarun Wadekar for (cb_idx = 0U; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
51e2469d82SVarun Wadekar val = tegra_smmu_read_32(smmu_id,
52e2469d82SVarun Wadekar ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx));
53e2469d82SVarun Wadekar val &= (uint32_t)~SMMU_CBn_ACTLR_CPRE_BIT;
54e2469d82SVarun Wadekar tegra_smmu_write_32(smmu_id, ctx_base +
55e2469d82SVarun Wadekar (SMMU_GSR0_PGSIZE_64K * cb_idx), val);
56e2469d82SVarun Wadekar }
57e2469d82SVarun Wadekar
58e2469d82SVarun Wadekar /* set CACHE LOCK bit for NS Aux. Config. Register */
59e2469d82SVarun Wadekar val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
60e2469d82SVarun Wadekar val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
61e2469d82SVarun Wadekar tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
62e2469d82SVarun Wadekar
63e2469d82SVarun Wadekar /* set CACHE LOCK bit for S Aux. Config. Register */
64e2469d82SVarun Wadekar val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
65e2469d82SVarun Wadekar val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
66e2469d82SVarun Wadekar tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
67e2469d82SVarun Wadekar }
68e2469d82SVarun Wadekar }
69*21ec61a9SVarun Wadekar
70*21ec61a9SVarun Wadekar /*
71*21ec61a9SVarun Wadekar * Verify SMMU settings have not been altered during boot
72*21ec61a9SVarun Wadekar */
tegra_smmu_verify(void)73*21ec61a9SVarun Wadekar void tegra_smmu_verify(void)
74*21ec61a9SVarun Wadekar {
75*21ec61a9SVarun Wadekar uint32_t cb_idx, ctx_base, smmu_id, val;
76*21ec61a9SVarun Wadekar uint32_t num_smmu_devices = plat_get_num_smmu_devices();
77*21ec61a9SVarun Wadekar uint32_t mismatch = 0U;
78*21ec61a9SVarun Wadekar
79*21ec61a9SVarun Wadekar for (smmu_id = 0U; smmu_id < num_smmu_devices; smmu_id++) {
80*21ec61a9SVarun Wadekar /* check PGSIZE_64K bit inr S Aux. Config. Register */
81*21ec61a9SVarun Wadekar val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
82*21ec61a9SVarun Wadekar if (0U == (val & SMMU_GSR0_PGSIZE_64K)) {
83*21ec61a9SVarun Wadekar ERROR("%s: PGSIZE_64K Mismatch - smmu_id=%d, GSR0_SECURE_ACR=%x\n",
84*21ec61a9SVarun Wadekar __func__, smmu_id, val);
85*21ec61a9SVarun Wadekar mismatch = MISMATCH_DETECTED;
86*21ec61a9SVarun Wadekar }
87*21ec61a9SVarun Wadekar
88*21ec61a9SVarun Wadekar /* check CACHE LOCK bit in S Aux. Config. Register */
89*21ec61a9SVarun Wadekar if (0U == (val & SMMU_ACR_CACHE_LOCK_ENABLE_BIT)) {
90*21ec61a9SVarun Wadekar ERROR("%s: CACHE_LOCK Mismatch - smmu_id=%d, GSR0_SECURE_ACR=%x\n",
91*21ec61a9SVarun Wadekar __func__, smmu_id, val);
92*21ec61a9SVarun Wadekar mismatch = MISMATCH_DETECTED;
93*21ec61a9SVarun Wadekar }
94*21ec61a9SVarun Wadekar
95*21ec61a9SVarun Wadekar /* check CACHE LOCK bit in NS Aux. Config. Register */
96*21ec61a9SVarun Wadekar val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
97*21ec61a9SVarun Wadekar if (0U == (val & SMMU_ACR_CACHE_LOCK_ENABLE_BIT)) {
98*21ec61a9SVarun Wadekar ERROR("%s: Mismatch - smmu_id=%d, GNSR_ACR=%x\n",
99*21ec61a9SVarun Wadekar __func__, smmu_id, val);
100*21ec61a9SVarun Wadekar mismatch = MISMATCH_DETECTED;
101*21ec61a9SVarun Wadekar }
102*21ec61a9SVarun Wadekar
103*21ec61a9SVarun Wadekar /* verify TCU prefetch for all contexts is disabled */
104*21ec61a9SVarun Wadekar ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) +
105*21ec61a9SVarun Wadekar SMMU_CBn_ACTLR;
106*21ec61a9SVarun Wadekar for (cb_idx = 0U; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
107*21ec61a9SVarun Wadekar val = tegra_smmu_read_32(smmu_id,
108*21ec61a9SVarun Wadekar ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx));
109*21ec61a9SVarun Wadekar if (0U != (val & SMMU_CBn_ACTLR_CPRE_BIT)) {
110*21ec61a9SVarun Wadekar ERROR("%s: Mismatch - smmu_id=%d, cb_idx=%d, GSR0_PGSIZE_64K=%x\n",
111*21ec61a9SVarun Wadekar __func__, smmu_id, cb_idx, val);
112*21ec61a9SVarun Wadekar mismatch = MISMATCH_DETECTED;
113*21ec61a9SVarun Wadekar }
114*21ec61a9SVarun Wadekar }
115*21ec61a9SVarun Wadekar }
116*21ec61a9SVarun Wadekar
117*21ec61a9SVarun Wadekar /* Treat configuration mismatch as fatal */
118*21ec61a9SVarun Wadekar if ((mismatch == MISMATCH_DETECTED) && tegra_platform_is_silicon()) {
119*21ec61a9SVarun Wadekar panic();
120*21ec61a9SVarun Wadekar }
121*21ec61a9SVarun Wadekar }
122