1*e2469d82SVarun Wadekar /* 2*e2469d82SVarun Wadekar * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*e2469d82SVarun Wadekar * 4*e2469d82SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5*e2469d82SVarun Wadekar */ 6*e2469d82SVarun Wadekar 7*e2469d82SVarun Wadekar #include <assert.h> 8*e2469d82SVarun Wadekar 9*e2469d82SVarun Wadekar #include <arch_helpers.h> 10*e2469d82SVarun Wadekar #include <cortex_a53.h> 11*e2469d82SVarun Wadekar #include <common/debug.h> 12*e2469d82SVarun Wadekar #include <drivers/delay_timer.h> 13*e2469d82SVarun Wadekar #include <lib/mmio.h> 14*e2469d82SVarun Wadekar 15*e2469d82SVarun Wadekar #include <flowctrl.h> 16*e2469d82SVarun Wadekar #include <lib/utils_def.h> 17*e2469d82SVarun Wadekar #include <pmc.h> 18*e2469d82SVarun Wadekar #include <tegra_def.h> 19*e2469d82SVarun Wadekar 20*e2469d82SVarun Wadekar #define CLK_RST_DEV_L_SET 0x300 21*e2469d82SVarun Wadekar #define CLK_RST_DEV_L_CLR 0x304 22*e2469d82SVarun Wadekar #define CLK_BPMP_RST (1 << 1) 23*e2469d82SVarun Wadekar 24*e2469d82SVarun Wadekar #define EVP_BPMP_RESET_VECTOR 0x200 25*e2469d82SVarun Wadekar 26*e2469d82SVarun Wadekar static const uint64_t flowctrl_offset_cpu_csr[4] = { 27*e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU0_CSR), 28*e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR), 29*e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 8), 30*e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 16) 31*e2469d82SVarun Wadekar }; 32*e2469d82SVarun Wadekar 33*e2469d82SVarun Wadekar static const uint64_t flowctrl_offset_halt_cpu[4] = { 34*e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU0_EVENTS), 35*e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS), 36*e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 8), 37*e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 16) 38*e2469d82SVarun Wadekar }; 39*e2469d82SVarun Wadekar 40*e2469d82SVarun Wadekar static const uint64_t flowctrl_offset_cc4_ctrl[4] = { 41*e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL), 42*e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 4), 43*e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 8), 44*e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 12) 45*e2469d82SVarun Wadekar }; 46*e2469d82SVarun Wadekar 47*e2469d82SVarun Wadekar static inline void tegra_fc_cc4_ctrl(int cpu_id, uint32_t val) 48*e2469d82SVarun Wadekar { 49*e2469d82SVarun Wadekar mmio_write_32(flowctrl_offset_cc4_ctrl[cpu_id], val); 50*e2469d82SVarun Wadekar val = mmio_read_32(flowctrl_offset_cc4_ctrl[cpu_id]); 51*e2469d82SVarun Wadekar } 52*e2469d82SVarun Wadekar 53*e2469d82SVarun Wadekar static inline void tegra_fc_cpu_csr(int cpu_id, uint32_t val) 54*e2469d82SVarun Wadekar { 55*e2469d82SVarun Wadekar mmio_write_32(flowctrl_offset_cpu_csr[cpu_id], val); 56*e2469d82SVarun Wadekar val = mmio_read_32(flowctrl_offset_cpu_csr[cpu_id]); 57*e2469d82SVarun Wadekar } 58*e2469d82SVarun Wadekar 59*e2469d82SVarun Wadekar static inline void tegra_fc_halt_cpu(int cpu_id, uint32_t val) 60*e2469d82SVarun Wadekar { 61*e2469d82SVarun Wadekar mmio_write_32(flowctrl_offset_halt_cpu[cpu_id], val); 62*e2469d82SVarun Wadekar val = mmio_read_32(flowctrl_offset_halt_cpu[cpu_id]); 63*e2469d82SVarun Wadekar } 64*e2469d82SVarun Wadekar 65*e2469d82SVarun Wadekar static void tegra_fc_prepare_suspend(int cpu_id, uint32_t csr) 66*e2469d82SVarun Wadekar { 67*e2469d82SVarun Wadekar uint32_t val; 68*e2469d82SVarun Wadekar 69*e2469d82SVarun Wadekar val = FLOWCTRL_HALT_GIC_IRQ | FLOWCTRL_HALT_GIC_FIQ | 70*e2469d82SVarun Wadekar FLOWCTRL_HALT_LIC_IRQ | FLOWCTRL_HALT_LIC_FIQ | 71*e2469d82SVarun Wadekar FLOWCTRL_WAITEVENT; 72*e2469d82SVarun Wadekar tegra_fc_halt_cpu(cpu_id, val); 73*e2469d82SVarun Wadekar 74*e2469d82SVarun Wadekar val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG | 75*e2469d82SVarun Wadekar FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu_id); 76*e2469d82SVarun Wadekar tegra_fc_cpu_csr(cpu_id, val | csr); 77*e2469d82SVarun Wadekar } 78*e2469d82SVarun Wadekar 79*e2469d82SVarun Wadekar /******************************************************************************* 80*e2469d82SVarun Wadekar * After this, no core can wake from C7 until the action is reverted. 81*e2469d82SVarun Wadekar * If a wake up event is asserted, the FC state machine will stall until 82*e2469d82SVarun Wadekar * the action is reverted. 83*e2469d82SVarun Wadekar ******************************************************************************/ 84*e2469d82SVarun Wadekar void tegra_fc_ccplex_pgexit_lock(void) 85*e2469d82SVarun Wadekar { 86*e2469d82SVarun Wadekar unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK; 87*e2469d82SVarun Wadekar uint32_t flags = tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT) & ~INTERCEPT_IRQ_PENDING;; 88*e2469d82SVarun Wadekar uint32_t icept_cpu_flags[] = { 89*e2469d82SVarun Wadekar INTERCEPT_EXIT_PG_CORE0, 90*e2469d82SVarun Wadekar INTERCEPT_EXIT_PG_CORE1, 91*e2469d82SVarun Wadekar INTERCEPT_EXIT_PG_CORE2, 92*e2469d82SVarun Wadekar INTERCEPT_EXIT_PG_CORE3 93*e2469d82SVarun Wadekar }; 94*e2469d82SVarun Wadekar 95*e2469d82SVarun Wadekar /* set the intercept flags */ 96*e2469d82SVarun Wadekar for (i = 0; i < ARRAY_SIZE(icept_cpu_flags); i++) { 97*e2469d82SVarun Wadekar 98*e2469d82SVarun Wadekar /* skip current CPU */ 99*e2469d82SVarun Wadekar if (i == cpu) 100*e2469d82SVarun Wadekar continue; 101*e2469d82SVarun Wadekar 102*e2469d82SVarun Wadekar /* enable power gate exit intercept locks */ 103*e2469d82SVarun Wadekar flags |= icept_cpu_flags[i]; 104*e2469d82SVarun Wadekar } 105*e2469d82SVarun Wadekar 106*e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_FC_SEQ_INTERCEPT, flags); 107*e2469d82SVarun Wadekar (void)tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT); 108*e2469d82SVarun Wadekar } 109*e2469d82SVarun Wadekar 110*e2469d82SVarun Wadekar /******************************************************************************* 111*e2469d82SVarun Wadekar * Revert the ccplex powergate exit locks 112*e2469d82SVarun Wadekar ******************************************************************************/ 113*e2469d82SVarun Wadekar void tegra_fc_ccplex_pgexit_unlock(void) 114*e2469d82SVarun Wadekar { 115*e2469d82SVarun Wadekar /* clear lock bits, clear pending interrupts */ 116*e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_FC_SEQ_INTERCEPT, INTERCEPT_IRQ_PENDING); 117*e2469d82SVarun Wadekar (void)tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT); 118*e2469d82SVarun Wadekar } 119*e2469d82SVarun Wadekar 120*e2469d82SVarun Wadekar /******************************************************************************* 121*e2469d82SVarun Wadekar * Powerdn the current CPU 122*e2469d82SVarun Wadekar ******************************************************************************/ 123*e2469d82SVarun Wadekar void tegra_fc_cpu_powerdn(uint32_t mpidr) 124*e2469d82SVarun Wadekar { 125*e2469d82SVarun Wadekar int cpu = mpidr & MPIDR_CPU_MASK; 126*e2469d82SVarun Wadekar 127*e2469d82SVarun Wadekar VERBOSE("CPU%d powering down...\n", cpu); 128*e2469d82SVarun Wadekar tegra_fc_prepare_suspend(cpu, 0); 129*e2469d82SVarun Wadekar } 130*e2469d82SVarun Wadekar 131*e2469d82SVarun Wadekar /******************************************************************************* 132*e2469d82SVarun Wadekar * Suspend the current CPU cluster 133*e2469d82SVarun Wadekar ******************************************************************************/ 134*e2469d82SVarun Wadekar void tegra_fc_cluster_idle(uint32_t mpidr) 135*e2469d82SVarun Wadekar { 136*e2469d82SVarun Wadekar int cpu = mpidr & MPIDR_CPU_MASK; 137*e2469d82SVarun Wadekar uint32_t val; 138*e2469d82SVarun Wadekar 139*e2469d82SVarun Wadekar VERBOSE("Entering cluster idle state...\n"); 140*e2469d82SVarun Wadekar 141*e2469d82SVarun Wadekar tegra_fc_cc4_ctrl(cpu, 0); 142*e2469d82SVarun Wadekar 143*e2469d82SVarun Wadekar /* hardware L2 flush is faster for A53 only */ 144*e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, 145*e2469d82SVarun Wadekar !!MPIDR_AFFLVL1_VAL(mpidr)); 146*e2469d82SVarun Wadekar 147*e2469d82SVarun Wadekar /* suspend the CPU cluster */ 148*e2469d82SVarun Wadekar val = FLOWCTRL_PG_CPU_NONCPU << FLOWCTRL_ENABLE_EXT; 149*e2469d82SVarun Wadekar tegra_fc_prepare_suspend(cpu, val); 150*e2469d82SVarun Wadekar } 151*e2469d82SVarun Wadekar 152*e2469d82SVarun Wadekar /******************************************************************************* 153*e2469d82SVarun Wadekar * Power down the current CPU cluster 154*e2469d82SVarun Wadekar ******************************************************************************/ 155*e2469d82SVarun Wadekar void tegra_fc_cluster_powerdn(uint32_t mpidr) 156*e2469d82SVarun Wadekar { 157*e2469d82SVarun Wadekar int cpu = mpidr & MPIDR_CPU_MASK; 158*e2469d82SVarun Wadekar uint32_t val; 159*e2469d82SVarun Wadekar 160*e2469d82SVarun Wadekar VERBOSE("Entering cluster powerdn state...\n"); 161*e2469d82SVarun Wadekar 162*e2469d82SVarun Wadekar tegra_fc_cc4_ctrl(cpu, 0); 163*e2469d82SVarun Wadekar 164*e2469d82SVarun Wadekar /* hardware L2 flush is faster for A53 only */ 165*e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, 166*e2469d82SVarun Wadekar read_midr() == CORTEX_A53_MIDR); 167*e2469d82SVarun Wadekar 168*e2469d82SVarun Wadekar /* power down the CPU cluster */ 169*e2469d82SVarun Wadekar val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT; 170*e2469d82SVarun Wadekar tegra_fc_prepare_suspend(cpu, val); 171*e2469d82SVarun Wadekar } 172*e2469d82SVarun Wadekar 173*e2469d82SVarun Wadekar /******************************************************************************* 174*e2469d82SVarun Wadekar * Check if cluster idle or power down state is allowed from this CPU 175*e2469d82SVarun Wadekar ******************************************************************************/ 176*e2469d82SVarun Wadekar bool tegra_fc_is_ccx_allowed(void) 177*e2469d82SVarun Wadekar { 178*e2469d82SVarun Wadekar unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK; 179*e2469d82SVarun Wadekar uint32_t val; 180*e2469d82SVarun Wadekar bool ccx_allowed = true; 181*e2469d82SVarun Wadekar 182*e2469d82SVarun Wadekar for (i = 0; i < ARRAY_SIZE(flowctrl_offset_cpu_csr); i++) { 183*e2469d82SVarun Wadekar 184*e2469d82SVarun Wadekar /* skip current CPU */ 185*e2469d82SVarun Wadekar if (i == cpu) 186*e2469d82SVarun Wadekar continue; 187*e2469d82SVarun Wadekar 188*e2469d82SVarun Wadekar /* check if all other CPUs are already halted */ 189*e2469d82SVarun Wadekar val = mmio_read_32(flowctrl_offset_cpu_csr[i]); 190*e2469d82SVarun Wadekar if ((val & FLOWCTRL_CSR_HALT_MASK) == 0U) { 191*e2469d82SVarun Wadekar ccx_allowed = false; 192*e2469d82SVarun Wadekar } 193*e2469d82SVarun Wadekar } 194*e2469d82SVarun Wadekar 195*e2469d82SVarun Wadekar return ccx_allowed; 196*e2469d82SVarun Wadekar } 197*e2469d82SVarun Wadekar 198*e2469d82SVarun Wadekar /******************************************************************************* 199*e2469d82SVarun Wadekar * Suspend the entire SoC 200*e2469d82SVarun Wadekar ******************************************************************************/ 201*e2469d82SVarun Wadekar void tegra_fc_soc_powerdn(uint32_t mpidr) 202*e2469d82SVarun Wadekar { 203*e2469d82SVarun Wadekar int cpu = mpidr & MPIDR_CPU_MASK; 204*e2469d82SVarun Wadekar uint32_t val; 205*e2469d82SVarun Wadekar 206*e2469d82SVarun Wadekar VERBOSE("Entering SoC powerdn state...\n"); 207*e2469d82SVarun Wadekar 208*e2469d82SVarun Wadekar tegra_fc_cc4_ctrl(cpu, 0); 209*e2469d82SVarun Wadekar 210*e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, 1); 211*e2469d82SVarun Wadekar 212*e2469d82SVarun Wadekar val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT; 213*e2469d82SVarun Wadekar tegra_fc_prepare_suspend(cpu, val); 214*e2469d82SVarun Wadekar 215*e2469d82SVarun Wadekar /* overwrite HALT register */ 216*e2469d82SVarun Wadekar tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT); 217*e2469d82SVarun Wadekar } 218*e2469d82SVarun Wadekar 219*e2469d82SVarun Wadekar /******************************************************************************* 220*e2469d82SVarun Wadekar * Power up the CPU 221*e2469d82SVarun Wadekar ******************************************************************************/ 222*e2469d82SVarun Wadekar void tegra_fc_cpu_on(int cpu) 223*e2469d82SVarun Wadekar { 224*e2469d82SVarun Wadekar tegra_fc_cpu_csr(cpu, FLOWCTRL_CSR_ENABLE); 225*e2469d82SVarun Wadekar tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT | FLOWCTRL_HALT_SCLK); 226*e2469d82SVarun Wadekar } 227*e2469d82SVarun Wadekar 228*e2469d82SVarun Wadekar /******************************************************************************* 229*e2469d82SVarun Wadekar * Power down the CPU 230*e2469d82SVarun Wadekar ******************************************************************************/ 231*e2469d82SVarun Wadekar void tegra_fc_cpu_off(int cpu) 232*e2469d82SVarun Wadekar { 233*e2469d82SVarun Wadekar uint32_t val; 234*e2469d82SVarun Wadekar 235*e2469d82SVarun Wadekar /* 236*e2469d82SVarun Wadekar * Flow controller powers down the CPU during wfi. The CPU would be 237*e2469d82SVarun Wadekar * powered on when it receives any interrupt. 238*e2469d82SVarun Wadekar */ 239*e2469d82SVarun Wadekar val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG | 240*e2469d82SVarun Wadekar FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu); 241*e2469d82SVarun Wadekar tegra_fc_cpu_csr(cpu, val); 242*e2469d82SVarun Wadekar tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT); 243*e2469d82SVarun Wadekar tegra_fc_cc4_ctrl(cpu, 0); 244*e2469d82SVarun Wadekar } 245*e2469d82SVarun Wadekar 246*e2469d82SVarun Wadekar /******************************************************************************* 247*e2469d82SVarun Wadekar * Inform the BPMP that we have completed the cluster power up 248*e2469d82SVarun Wadekar ******************************************************************************/ 249*e2469d82SVarun Wadekar void tegra_fc_lock_active_cluster(void) 250*e2469d82SVarun Wadekar { 251*e2469d82SVarun Wadekar uint32_t val; 252*e2469d82SVarun Wadekar 253*e2469d82SVarun Wadekar val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL); 254*e2469d82SVarun Wadekar val |= FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK; 255*e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_BPMP_CLUSTER_CONTROL, val); 256*e2469d82SVarun Wadekar val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL); 257*e2469d82SVarun Wadekar } 258*e2469d82SVarun Wadekar 259*e2469d82SVarun Wadekar /******************************************************************************* 260*e2469d82SVarun Wadekar * Power ON BPMP processor 261*e2469d82SVarun Wadekar ******************************************************************************/ 262*e2469d82SVarun Wadekar void tegra_fc_bpmp_on(uint32_t entrypoint) 263*e2469d82SVarun Wadekar { 264*e2469d82SVarun Wadekar /* halt BPMP */ 265*e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, FLOWCTRL_WAITEVENT); 266*e2469d82SVarun Wadekar 267*e2469d82SVarun Wadekar /* Assert BPMP reset */ 268*e2469d82SVarun Wadekar mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_SET, CLK_BPMP_RST); 269*e2469d82SVarun Wadekar 270*e2469d82SVarun Wadekar /* Set reset address (stored in PMC_SCRATCH39) */ 271*e2469d82SVarun Wadekar mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, entrypoint); 272*e2469d82SVarun Wadekar while (entrypoint != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR)) 273*e2469d82SVarun Wadekar ; /* wait till value reaches EVP_BPMP_RESET_VECTOR */ 274*e2469d82SVarun Wadekar 275*e2469d82SVarun Wadekar /* Wait for 2us before de-asserting the reset signal. */ 276*e2469d82SVarun Wadekar udelay(2); 277*e2469d82SVarun Wadekar 278*e2469d82SVarun Wadekar /* De-assert BPMP reset */ 279*e2469d82SVarun Wadekar mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_CLR, CLK_BPMP_RST); 280*e2469d82SVarun Wadekar 281*e2469d82SVarun Wadekar /* Un-halt BPMP */ 282*e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, 0); 283*e2469d82SVarun Wadekar } 284*e2469d82SVarun Wadekar 285*e2469d82SVarun Wadekar /******************************************************************************* 286*e2469d82SVarun Wadekar * Power OFF BPMP processor 287*e2469d82SVarun Wadekar ******************************************************************************/ 288*e2469d82SVarun Wadekar void tegra_fc_bpmp_off(void) 289*e2469d82SVarun Wadekar { 290*e2469d82SVarun Wadekar /* halt BPMP */ 291*e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, FLOWCTRL_WAITEVENT); 292*e2469d82SVarun Wadekar 293*e2469d82SVarun Wadekar /* Assert BPMP reset */ 294*e2469d82SVarun Wadekar mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_SET, CLK_BPMP_RST); 295*e2469d82SVarun Wadekar 296*e2469d82SVarun Wadekar /* Clear reset address */ 297*e2469d82SVarun Wadekar mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, 0); 298*e2469d82SVarun Wadekar while (0 != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR)) 299*e2469d82SVarun Wadekar ; /* wait till value reaches EVP_BPMP_RESET_VECTOR */ 300*e2469d82SVarun Wadekar } 301*e2469d82SVarun Wadekar 302*e2469d82SVarun Wadekar /******************************************************************************* 303*e2469d82SVarun Wadekar * Route legacy FIQ to the GICD 304*e2469d82SVarun Wadekar ******************************************************************************/ 305*e2469d82SVarun Wadekar void tegra_fc_enable_fiq_to_ccplex_routing(void) 306*e2469d82SVarun Wadekar { 307*e2469d82SVarun Wadekar uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL); 308*e2469d82SVarun Wadekar 309*e2469d82SVarun Wadekar /* set the bit to pass FIQs to the GICD */ 310*e2469d82SVarun Wadekar tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val | FLOWCTRL_FIQ2CCPLEX_ENABLE); 311*e2469d82SVarun Wadekar } 312*e2469d82SVarun Wadekar 313*e2469d82SVarun Wadekar /******************************************************************************* 314*e2469d82SVarun Wadekar * Disable routing legacy FIQ to the GICD 315*e2469d82SVarun Wadekar ******************************************************************************/ 316*e2469d82SVarun Wadekar void tegra_fc_disable_fiq_to_ccplex_routing(void) 317*e2469d82SVarun Wadekar { 318*e2469d82SVarun Wadekar uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL); 319*e2469d82SVarun Wadekar 320*e2469d82SVarun Wadekar /* clear the bit to pass FIQs to the GICD */ 321*e2469d82SVarun Wadekar tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val & ~FLOWCTRL_FIQ2CCPLEX_ENABLE); 322*e2469d82SVarun Wadekar } 323