1e2469d82SVarun Wadekar /* 2e2469d82SVarun Wadekar * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3e2469d82SVarun Wadekar * 4e2469d82SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5e2469d82SVarun Wadekar */ 6e2469d82SVarun Wadekar 7e2469d82SVarun Wadekar #include <assert.h> 8e2469d82SVarun Wadekar 9e2469d82SVarun Wadekar #include <arch_helpers.h> 10e2469d82SVarun Wadekar #include <cortex_a53.h> 11e2469d82SVarun Wadekar #include <common/debug.h> 12e2469d82SVarun Wadekar #include <drivers/delay_timer.h> 13e2469d82SVarun Wadekar #include <lib/mmio.h> 14e2469d82SVarun Wadekar 15e2469d82SVarun Wadekar #include <flowctrl.h> 16e2469d82SVarun Wadekar #include <lib/utils_def.h> 17e2469d82SVarun Wadekar #include <pmc.h> 18e2469d82SVarun Wadekar #include <tegra_def.h> 19e2469d82SVarun Wadekar 20e2469d82SVarun Wadekar #define CLK_RST_DEV_L_SET 0x300 21e2469d82SVarun Wadekar #define CLK_RST_DEV_L_CLR 0x304 22e2469d82SVarun Wadekar #define CLK_BPMP_RST (1 << 1) 23e2469d82SVarun Wadekar 24e2469d82SVarun Wadekar #define EVP_BPMP_RESET_VECTOR 0x200 25e2469d82SVarun Wadekar 26e2469d82SVarun Wadekar static const uint64_t flowctrl_offset_cpu_csr[4] = { 27e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU0_CSR), 28e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR), 29e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 8), 30e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 16) 31e2469d82SVarun Wadekar }; 32e2469d82SVarun Wadekar 33e2469d82SVarun Wadekar static const uint64_t flowctrl_offset_halt_cpu[4] = { 34e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU0_EVENTS), 35e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS), 36e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 8), 37e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 16) 38e2469d82SVarun Wadekar }; 39e2469d82SVarun Wadekar 40e2469d82SVarun Wadekar static const uint64_t flowctrl_offset_cc4_ctrl[4] = { 41e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL), 42e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 4), 43e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 8), 44e2469d82SVarun Wadekar (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 12) 45e2469d82SVarun Wadekar }; 46e2469d82SVarun Wadekar 47e2469d82SVarun Wadekar static inline void tegra_fc_cc4_ctrl(int cpu_id, uint32_t val) 48e2469d82SVarun Wadekar { 49e2469d82SVarun Wadekar mmio_write_32(flowctrl_offset_cc4_ctrl[cpu_id], val); 50e2469d82SVarun Wadekar val = mmio_read_32(flowctrl_offset_cc4_ctrl[cpu_id]); 51e2469d82SVarun Wadekar } 52e2469d82SVarun Wadekar 53e2469d82SVarun Wadekar static inline void tegra_fc_cpu_csr(int cpu_id, uint32_t val) 54e2469d82SVarun Wadekar { 55e2469d82SVarun Wadekar mmio_write_32(flowctrl_offset_cpu_csr[cpu_id], val); 56e2469d82SVarun Wadekar val = mmio_read_32(flowctrl_offset_cpu_csr[cpu_id]); 57e2469d82SVarun Wadekar } 58e2469d82SVarun Wadekar 59e2469d82SVarun Wadekar static inline void tegra_fc_halt_cpu(int cpu_id, uint32_t val) 60e2469d82SVarun Wadekar { 61e2469d82SVarun Wadekar mmio_write_32(flowctrl_offset_halt_cpu[cpu_id], val); 62e2469d82SVarun Wadekar val = mmio_read_32(flowctrl_offset_halt_cpu[cpu_id]); 63e2469d82SVarun Wadekar } 64e2469d82SVarun Wadekar 65e2469d82SVarun Wadekar static void tegra_fc_prepare_suspend(int cpu_id, uint32_t csr) 66e2469d82SVarun Wadekar { 67e2469d82SVarun Wadekar uint32_t val; 68e2469d82SVarun Wadekar 69e2469d82SVarun Wadekar val = FLOWCTRL_HALT_GIC_IRQ | FLOWCTRL_HALT_GIC_FIQ | 70e2469d82SVarun Wadekar FLOWCTRL_HALT_LIC_IRQ | FLOWCTRL_HALT_LIC_FIQ | 71e2469d82SVarun Wadekar FLOWCTRL_WAITEVENT; 72e2469d82SVarun Wadekar tegra_fc_halt_cpu(cpu_id, val); 73e2469d82SVarun Wadekar 74e2469d82SVarun Wadekar val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG | 75e2469d82SVarun Wadekar FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu_id); 76e2469d82SVarun Wadekar tegra_fc_cpu_csr(cpu_id, val | csr); 77e2469d82SVarun Wadekar } 78e2469d82SVarun Wadekar 79e2469d82SVarun Wadekar /******************************************************************************* 80e2469d82SVarun Wadekar * After this, no core can wake from C7 until the action is reverted. 81e2469d82SVarun Wadekar * If a wake up event is asserted, the FC state machine will stall until 82e2469d82SVarun Wadekar * the action is reverted. 83e2469d82SVarun Wadekar ******************************************************************************/ 84e2469d82SVarun Wadekar void tegra_fc_ccplex_pgexit_lock(void) 85e2469d82SVarun Wadekar { 86e2469d82SVarun Wadekar unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK; 87*9a90d720SElyes Haouas uint32_t flags = tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT) & ~INTERCEPT_IRQ_PENDING; 88e2469d82SVarun Wadekar uint32_t icept_cpu_flags[] = { 89e2469d82SVarun Wadekar INTERCEPT_EXIT_PG_CORE0, 90e2469d82SVarun Wadekar INTERCEPT_EXIT_PG_CORE1, 91e2469d82SVarun Wadekar INTERCEPT_EXIT_PG_CORE2, 92e2469d82SVarun Wadekar INTERCEPT_EXIT_PG_CORE3 93e2469d82SVarun Wadekar }; 94e2469d82SVarun Wadekar 95e2469d82SVarun Wadekar /* set the intercept flags */ 96e2469d82SVarun Wadekar for (i = 0; i < ARRAY_SIZE(icept_cpu_flags); i++) { 97e2469d82SVarun Wadekar 98e2469d82SVarun Wadekar /* skip current CPU */ 99e2469d82SVarun Wadekar if (i == cpu) 100e2469d82SVarun Wadekar continue; 101e2469d82SVarun Wadekar 102e2469d82SVarun Wadekar /* enable power gate exit intercept locks */ 103e2469d82SVarun Wadekar flags |= icept_cpu_flags[i]; 104e2469d82SVarun Wadekar } 105e2469d82SVarun Wadekar 106e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_FC_SEQ_INTERCEPT, flags); 107e2469d82SVarun Wadekar (void)tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT); 108e2469d82SVarun Wadekar } 109e2469d82SVarun Wadekar 110e2469d82SVarun Wadekar /******************************************************************************* 111e2469d82SVarun Wadekar * Revert the ccplex powergate exit locks 112e2469d82SVarun Wadekar ******************************************************************************/ 113e2469d82SVarun Wadekar void tegra_fc_ccplex_pgexit_unlock(void) 114e2469d82SVarun Wadekar { 115e2469d82SVarun Wadekar /* clear lock bits, clear pending interrupts */ 116e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_FC_SEQ_INTERCEPT, INTERCEPT_IRQ_PENDING); 117e2469d82SVarun Wadekar (void)tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT); 118e2469d82SVarun Wadekar } 119e2469d82SVarun Wadekar 120e2469d82SVarun Wadekar /******************************************************************************* 121e2469d82SVarun Wadekar * Powerdn the current CPU 122e2469d82SVarun Wadekar ******************************************************************************/ 123e2469d82SVarun Wadekar void tegra_fc_cpu_powerdn(uint32_t mpidr) 124e2469d82SVarun Wadekar { 125e2469d82SVarun Wadekar int cpu = mpidr & MPIDR_CPU_MASK; 126e2469d82SVarun Wadekar 127e2469d82SVarun Wadekar VERBOSE("CPU%d powering down...\n", cpu); 128e2469d82SVarun Wadekar tegra_fc_prepare_suspend(cpu, 0); 129e2469d82SVarun Wadekar } 130e2469d82SVarun Wadekar 131e2469d82SVarun Wadekar /******************************************************************************* 132e2469d82SVarun Wadekar * Suspend the current CPU cluster 133e2469d82SVarun Wadekar ******************************************************************************/ 134e2469d82SVarun Wadekar void tegra_fc_cluster_idle(uint32_t mpidr) 135e2469d82SVarun Wadekar { 136e2469d82SVarun Wadekar int cpu = mpidr & MPIDR_CPU_MASK; 137e2469d82SVarun Wadekar uint32_t val; 138e2469d82SVarun Wadekar 139e2469d82SVarun Wadekar VERBOSE("Entering cluster idle state...\n"); 140e2469d82SVarun Wadekar 141e2469d82SVarun Wadekar tegra_fc_cc4_ctrl(cpu, 0); 142e2469d82SVarun Wadekar 143e2469d82SVarun Wadekar /* hardware L2 flush is faster for A53 only */ 144e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, 145e2469d82SVarun Wadekar !!MPIDR_AFFLVL1_VAL(mpidr)); 146e2469d82SVarun Wadekar 147e2469d82SVarun Wadekar /* suspend the CPU cluster */ 148e2469d82SVarun Wadekar val = FLOWCTRL_PG_CPU_NONCPU << FLOWCTRL_ENABLE_EXT; 149e2469d82SVarun Wadekar tegra_fc_prepare_suspend(cpu, val); 150e2469d82SVarun Wadekar } 151e2469d82SVarun Wadekar 152e2469d82SVarun Wadekar /******************************************************************************* 153e2469d82SVarun Wadekar * Power down the current CPU cluster 154e2469d82SVarun Wadekar ******************************************************************************/ 155e2469d82SVarun Wadekar void tegra_fc_cluster_powerdn(uint32_t mpidr) 156e2469d82SVarun Wadekar { 157e2469d82SVarun Wadekar int cpu = mpidr & MPIDR_CPU_MASK; 158e2469d82SVarun Wadekar uint32_t val; 159e2469d82SVarun Wadekar 160e2469d82SVarun Wadekar VERBOSE("Entering cluster powerdn state...\n"); 161e2469d82SVarun Wadekar 162e2469d82SVarun Wadekar tegra_fc_cc4_ctrl(cpu, 0); 163e2469d82SVarun Wadekar 164e2469d82SVarun Wadekar /* hardware L2 flush is faster for A53 only */ 165e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, 166e2469d82SVarun Wadekar read_midr() == CORTEX_A53_MIDR); 167e2469d82SVarun Wadekar 168e2469d82SVarun Wadekar /* power down the CPU cluster */ 169e2469d82SVarun Wadekar val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT; 170e2469d82SVarun Wadekar tegra_fc_prepare_suspend(cpu, val); 171e2469d82SVarun Wadekar } 172e2469d82SVarun Wadekar 173e2469d82SVarun Wadekar /******************************************************************************* 174e2469d82SVarun Wadekar * Check if cluster idle or power down state is allowed from this CPU 175e2469d82SVarun Wadekar ******************************************************************************/ 176e2469d82SVarun Wadekar bool tegra_fc_is_ccx_allowed(void) 177e2469d82SVarun Wadekar { 178e2469d82SVarun Wadekar unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK; 179e2469d82SVarun Wadekar uint32_t val; 180e2469d82SVarun Wadekar bool ccx_allowed = true; 181e2469d82SVarun Wadekar 182e2469d82SVarun Wadekar for (i = 0; i < ARRAY_SIZE(flowctrl_offset_cpu_csr); i++) { 183e2469d82SVarun Wadekar 184e2469d82SVarun Wadekar /* skip current CPU */ 185e2469d82SVarun Wadekar if (i == cpu) 186e2469d82SVarun Wadekar continue; 187e2469d82SVarun Wadekar 188e2469d82SVarun Wadekar /* check if all other CPUs are already halted */ 189e2469d82SVarun Wadekar val = mmio_read_32(flowctrl_offset_cpu_csr[i]); 190e2469d82SVarun Wadekar if ((val & FLOWCTRL_CSR_HALT_MASK) == 0U) { 191e2469d82SVarun Wadekar ccx_allowed = false; 192e2469d82SVarun Wadekar } 193e2469d82SVarun Wadekar } 194e2469d82SVarun Wadekar 195e2469d82SVarun Wadekar return ccx_allowed; 196e2469d82SVarun Wadekar } 197e2469d82SVarun Wadekar 198e2469d82SVarun Wadekar /******************************************************************************* 199e2469d82SVarun Wadekar * Suspend the entire SoC 200e2469d82SVarun Wadekar ******************************************************************************/ 201e2469d82SVarun Wadekar void tegra_fc_soc_powerdn(uint32_t mpidr) 202e2469d82SVarun Wadekar { 203e2469d82SVarun Wadekar int cpu = mpidr & MPIDR_CPU_MASK; 204e2469d82SVarun Wadekar uint32_t val; 205e2469d82SVarun Wadekar 206e2469d82SVarun Wadekar VERBOSE("Entering SoC powerdn state...\n"); 207e2469d82SVarun Wadekar 208e2469d82SVarun Wadekar tegra_fc_cc4_ctrl(cpu, 0); 209e2469d82SVarun Wadekar 210e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, 1); 211e2469d82SVarun Wadekar 212e2469d82SVarun Wadekar val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT; 213e2469d82SVarun Wadekar tegra_fc_prepare_suspend(cpu, val); 214e2469d82SVarun Wadekar 215e2469d82SVarun Wadekar /* overwrite HALT register */ 216e2469d82SVarun Wadekar tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT); 217e2469d82SVarun Wadekar } 218e2469d82SVarun Wadekar 219e2469d82SVarun Wadekar /******************************************************************************* 220e2469d82SVarun Wadekar * Power up the CPU 221e2469d82SVarun Wadekar ******************************************************************************/ 222e2469d82SVarun Wadekar void tegra_fc_cpu_on(int cpu) 223e2469d82SVarun Wadekar { 224e2469d82SVarun Wadekar tegra_fc_cpu_csr(cpu, FLOWCTRL_CSR_ENABLE); 225e2469d82SVarun Wadekar tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT | FLOWCTRL_HALT_SCLK); 226e2469d82SVarun Wadekar } 227e2469d82SVarun Wadekar 228e2469d82SVarun Wadekar /******************************************************************************* 229e2469d82SVarun Wadekar * Power down the CPU 230e2469d82SVarun Wadekar ******************************************************************************/ 231e2469d82SVarun Wadekar void tegra_fc_cpu_off(int cpu) 232e2469d82SVarun Wadekar { 233e2469d82SVarun Wadekar uint32_t val; 234e2469d82SVarun Wadekar 235e2469d82SVarun Wadekar /* 236e2469d82SVarun Wadekar * Flow controller powers down the CPU during wfi. The CPU would be 237e2469d82SVarun Wadekar * powered on when it receives any interrupt. 238e2469d82SVarun Wadekar */ 239e2469d82SVarun Wadekar val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG | 240e2469d82SVarun Wadekar FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu); 241e2469d82SVarun Wadekar tegra_fc_cpu_csr(cpu, val); 242e2469d82SVarun Wadekar tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT); 243e2469d82SVarun Wadekar tegra_fc_cc4_ctrl(cpu, 0); 244e2469d82SVarun Wadekar } 245e2469d82SVarun Wadekar 246e2469d82SVarun Wadekar /******************************************************************************* 247e2469d82SVarun Wadekar * Inform the BPMP that we have completed the cluster power up 248e2469d82SVarun Wadekar ******************************************************************************/ 249e2469d82SVarun Wadekar void tegra_fc_lock_active_cluster(void) 250e2469d82SVarun Wadekar { 251e2469d82SVarun Wadekar uint32_t val; 252e2469d82SVarun Wadekar 253e2469d82SVarun Wadekar val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL); 254e2469d82SVarun Wadekar val |= FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK; 255e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_BPMP_CLUSTER_CONTROL, val); 256e2469d82SVarun Wadekar val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL); 257e2469d82SVarun Wadekar } 258e2469d82SVarun Wadekar 259e2469d82SVarun Wadekar /******************************************************************************* 260e2469d82SVarun Wadekar * Power ON BPMP processor 261e2469d82SVarun Wadekar ******************************************************************************/ 262e2469d82SVarun Wadekar void tegra_fc_bpmp_on(uint32_t entrypoint) 263e2469d82SVarun Wadekar { 264e2469d82SVarun Wadekar /* halt BPMP */ 265e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, FLOWCTRL_WAITEVENT); 266e2469d82SVarun Wadekar 267e2469d82SVarun Wadekar /* Assert BPMP reset */ 268e2469d82SVarun Wadekar mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_SET, CLK_BPMP_RST); 269e2469d82SVarun Wadekar 270e2469d82SVarun Wadekar /* Set reset address (stored in PMC_SCRATCH39) */ 271e2469d82SVarun Wadekar mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, entrypoint); 272e2469d82SVarun Wadekar while (entrypoint != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR)) 273e2469d82SVarun Wadekar ; /* wait till value reaches EVP_BPMP_RESET_VECTOR */ 274e2469d82SVarun Wadekar 275e2469d82SVarun Wadekar /* Wait for 2us before de-asserting the reset signal. */ 276e2469d82SVarun Wadekar udelay(2); 277e2469d82SVarun Wadekar 278e2469d82SVarun Wadekar /* De-assert BPMP reset */ 279e2469d82SVarun Wadekar mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_CLR, CLK_BPMP_RST); 280e2469d82SVarun Wadekar 281e2469d82SVarun Wadekar /* Un-halt BPMP */ 282e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, 0); 283e2469d82SVarun Wadekar } 284e2469d82SVarun Wadekar 285e2469d82SVarun Wadekar /******************************************************************************* 286e2469d82SVarun Wadekar * Power OFF BPMP processor 287e2469d82SVarun Wadekar ******************************************************************************/ 288e2469d82SVarun Wadekar void tegra_fc_bpmp_off(void) 289e2469d82SVarun Wadekar { 290e2469d82SVarun Wadekar /* halt BPMP */ 291e2469d82SVarun Wadekar tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, FLOWCTRL_WAITEVENT); 292e2469d82SVarun Wadekar 293e2469d82SVarun Wadekar /* Assert BPMP reset */ 294e2469d82SVarun Wadekar mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_SET, CLK_BPMP_RST); 295e2469d82SVarun Wadekar 296e2469d82SVarun Wadekar /* Clear reset address */ 297e2469d82SVarun Wadekar mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, 0); 298e2469d82SVarun Wadekar while (0 != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR)) 299e2469d82SVarun Wadekar ; /* wait till value reaches EVP_BPMP_RESET_VECTOR */ 300e2469d82SVarun Wadekar } 301e2469d82SVarun Wadekar 302e2469d82SVarun Wadekar /******************************************************************************* 303e2469d82SVarun Wadekar * Route legacy FIQ to the GICD 304e2469d82SVarun Wadekar ******************************************************************************/ 305e2469d82SVarun Wadekar void tegra_fc_enable_fiq_to_ccplex_routing(void) 306e2469d82SVarun Wadekar { 307e2469d82SVarun Wadekar uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL); 308e2469d82SVarun Wadekar 309e2469d82SVarun Wadekar /* set the bit to pass FIQs to the GICD */ 310e2469d82SVarun Wadekar tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val | FLOWCTRL_FIQ2CCPLEX_ENABLE); 311e2469d82SVarun Wadekar } 312e2469d82SVarun Wadekar 313e2469d82SVarun Wadekar /******************************************************************************* 314e2469d82SVarun Wadekar * Disable routing legacy FIQ to the GICD 315e2469d82SVarun Wadekar ******************************************************************************/ 316e2469d82SVarun Wadekar void tegra_fc_disable_fiq_to_ccplex_routing(void) 317e2469d82SVarun Wadekar { 318e2469d82SVarun Wadekar uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL); 319e2469d82SVarun Wadekar 320e2469d82SVarun Wadekar /* clear the bit to pass FIQs to the GICD */ 321e2469d82SVarun Wadekar tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val & ~FLOWCTRL_FIQ2CCPLEX_ENABLE); 322e2469d82SVarun Wadekar } 323