1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <context_mgmt.h> 36 #include <debug.h> 37 #include <errno.h> 38 #include <memctrl.h> 39 #include <runtime_svc.h> 40 #include <tegra_private.h> 41 42 #define NS_SWITCH_AARCH32 1 43 #define SCR_RW_BITPOS __builtin_ctz(SCR_RW_BIT) 44 45 /******************************************************************************* 46 * Tegra SiP SMCs 47 ******************************************************************************/ 48 #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 49 #define TEGRA_SIP_AARCH_SWITCH 0x82000004 50 51 /******************************************************************************* 52 * SPSR settings for AARCH32/AARCH64 modes 53 ******************************************************************************/ 54 #define SPSR32 SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, \ 55 DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT) 56 #define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS) 57 58 /******************************************************************************* 59 * This function is responsible for handling all SiP calls from the NS world 60 ******************************************************************************/ 61 uint64_t tegra_sip_handler(uint32_t smc_fid, 62 uint64_t x1, 63 uint64_t x2, 64 uint64_t x3, 65 uint64_t x4, 66 void *cookie, 67 void *handle, 68 uint64_t flags) 69 { 70 uint32_t ns; 71 int err; 72 73 /* Determine which security state this SMC originated from */ 74 ns = is_caller_non_secure(flags); 75 if (!ns) 76 SMC_RET1(handle, SMC_UNK); 77 78 switch (smc_fid) { 79 80 case TEGRA_SIP_NEW_VIDEOMEM_REGION: 81 82 /* clean up the high bits */ 83 x1 = (uint32_t)x1; 84 x2 = (uint32_t)x2; 85 86 /* 87 * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) 88 * or falls outside of the valid DRAM range 89 */ 90 err = bl31_check_ns_address(x1, x2); 91 if (err) 92 SMC_RET1(handle, err); 93 94 /* 95 * Check if Video Memory is aligned to 1MB. 96 */ 97 if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { 98 ERROR("Unaligned Video Memory base address!\n"); 99 SMC_RET1(handle, -ENOTSUP); 100 } 101 102 /* new video memory carveout settings */ 103 tegra_memctrl_videomem_setup(x1, x2); 104 105 SMC_RET1(handle, 0); 106 break; 107 108 case TEGRA_SIP_AARCH_SWITCH: 109 110 /* clean up the high bits */ 111 x1 = (uint32_t)x1; 112 x2 = (uint32_t)x2; 113 114 if (!x1 || x2 > NS_SWITCH_AARCH32) { 115 ERROR("%s: invalid parameters\n", __func__); 116 SMC_RET1(handle, SMC_UNK); 117 } 118 119 /* x1 = ns entry point */ 120 cm_set_elr_spsr_el3(NON_SECURE, x1, 121 (x2 == NS_SWITCH_AARCH32) ? SPSR32 : SPSR64); 122 123 /* switch NS world mode */ 124 cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2); 125 126 INFO("CPU switched to AARCH%s mode\n", 127 (x2 == NS_SWITCH_AARCH32) ? "32" : "64"); 128 SMC_RET1(handle, 0); 129 break; 130 131 default: 132 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 133 break; 134 } 135 136 SMC_RET1(handle, SMC_UNK); 137 } 138 139 /* Define a runtime service descriptor for fast SMC calls */ 140 DECLARE_RT_SVC( 141 tegra_sip_fast, 142 143 OEN_SIP_START, 144 OEN_SIP_END, 145 SMC_TYPE_FAST, 146 NULL, 147 tegra_sip_handler 148 ); 149